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ADS54J42: What to do with unconnected JESD lanes?

Björn Langels
Intellectual 440 points

Part Number: ADS54J42

We have a problem with a high 100MHz signal picked up in our readings when clocking the ADC with 400MHz in a configuration where we use only 4 out of the 8 available JESD lanes.

When trying to find the source of the 100MHz using a spectrum analyzer we see a strong 100MHz emitting form the middle of the circuit and very, very strong 100MHz on the unused JESD lanes.

Are we supposed to terminate the unused lanes in any way, or maybe ground them? They are left open as the datasheet states nothing of what to do and all examples designs we have found always have all lanes connected to an FPGA or similar.

Do you have any suggestion of what normally cause this kind of problem?

We have a 100MHz, synchronous to the 400MHz clocking the ADC, present on our board and the receiving FPGA is klocked by the 100MHz, i.e. SYSREF is created using this FPGA clock as well as the SPI communication.

  • 0
    TI__Genius 12780 points
    Hi Bjorn,

    We are taking a look into your question, and will be back with you soon.

    Best Regards,

    Dan
  • 0 in reply to dBrock
    TI__Guru* 91947 points

    Bjorn,

    Are we supposed to terminate the unused lanes in any way, or maybe ground them?  You can leave these open,

    Do you have any suggestion of what normally cause this kind of problem?

    1. Do you turn off SYSREF after the link is configured? What is the SYSREF frequency?

    2. If you change the reference frequency to another value, does the issue track this frequency?

    3. Are any of your clocks or reference traces close to the analog input traces?

    If you would like to send your board schematic and layout files, we can take a look at it and maybe offer more suggestions.

    Regards,

    Jim

  • 0 in reply to jim s
    Intellectual 440 points

    Hello again Jim!
    Thank you for your reply.

    If I turn off SYSREF there is no change at all in the size of the 100MHz. Therefore I guess the frequency of the SYSREF is not an issue?
    I see no change in the sampled spectrum and I see no change when measuring on the unconnected JESD lanes with a spectrumanalyser.
    It is a bit tricky to change the SYSREF frequency as it is hard coeded in an FPGA and trimmed to be correctly timed regarding the flanks of the 400MHz clock.

    The frequency we see is EXACT 100MHz and exactly correlated to the 400/100MHz clock we use as system clock.The SYSREF frequency is 1.5625MHz

    Our design use an extremely sensitive amplifier to sample very small amounts of light arriving to a photo diod.
    We expect the amplifiers to pick up ambient noise, wi just did not expect the 100MHz to so strong on the unconnected pins.
    We also expect some 100MHz due to the four interleaving ADC but we rule that out as the cause due to the relatively hi amplitude of the 100MHz.

    We have also tested to terminate the unused JESD-lanes with 100OHm resistors. The measured spectrum measured on the lanes was reduced a bit but it did not have any effect on the picked up 100MHz on the sampled data.
    We have not dared to ground them as they will probably be active when the ADC power up and it is undocumented what happens if we do.

    We have tried to separate the sensitive parts as much as possible from any known source of noise, including metall shields around the amplifier and sensor.

    Our solution will probably be to cancel out the 100MHz in software by adding a correctional values to every quadruple of samples, which is possible as the 100MHz is exactly aligned with the 400MHz sample clock. We just have to measure the phase correlation and amplitude and use that as input to calculate the correctional values.

    We wanted your input before we send our, hopefully, last layout to production... 

    Regards
    Björn