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ADS5444: About the CLK voltage range of the AD converter

Teruo Kuwabara
Prodigy 50 points
Part Number: ADS5444

I would like to use ADS 5444.
In the data sheet, the absolute maximum rating is written as "Clock input to GND - 0.3 V to AVDD + 0.3 V". However, according to Figure 16 Single Ended Clock in single ended CLK example, a negative voltage is input It seems to be like it. Clock input to GND - 0.3 V to AVDD + 0.3 V Where does it refer?

  • 0
    TI__Genius 12780 points
    Hi Teruo,

    Figure 16 is referring to the analog input signal. If you look at Figures 24 through 26, you will see that the clock signal is not negative in the performance measurements.

    Best Regards,

    Dan
  • 0 in reply to dBrock
    Prodigy 50 points

    hi Daniel


    Thank you for answering
    I'm sorry. It seems that the material at hand was old.
    It does not seem to be a corresponding figure in ADS 5444 (REV.A).
    (Figure 36. Single-Ended Clock in REV.A)
    Would you please tell me the address of the document

  • 0 in reply to Teruo Kuwabara
    TI__Genius 12780 points

    Hi Teruo,

    Here is a link to the data sheet that I was looking at 

    Figure 36 here

    shows the positive clock input receiving the clock signal, and the negative clock input being tied to ground (0V). Further down in the data sheet, it states that the common-mode voltage of 2.4V is provided internally to the clock inputs.

    Since the AVDD should be 5V, you should not have an issue with keeping the clock signal positive. I hope this answered your question.

    Best Regards,

    Dan

  • 0 in reply to dBrock
    Prodigy 50 points
    hi Daniel

    All doubts were solved.
    thank you for your answer.