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ADS5421: Input Signal Beyond the Rails

Part Number: ADS5421

Hello,

I'm driving the analog input signal beyond the reference rail of the ADS5421.    My reference voltages are as follows:

VREFT = 3.5V  (Externally driven with unbuffered series reference)

VREFB = 1.5V (Externally driven with op-amp buffered reference)

CM = 2.5V

The single ended voltage at the analog input pin (IN - PIN59) is a pulse with amplitude ~= 3.7V.   I'm noticing that the preceeding sample dips negative.   Is this expected operation when driving the analog input beyond the reference rails?

Also, what are the min/max limits that we can drive VREFT and VREFB at?    Would it be possible to source VREFT with 3.9V and VREFB with 1.1V?

Don

  • Hi Don,

    The only documentation that we have for the ADS5421 is the datasheet.

    On page 3, the datasheet states that the difference between VREFT and VREFB must not exceed 2.025V,

    so setting VREFT and VREFB to 3.9V and 1.1V, respectively, should not be done. Additionally, Table 1 on page 13, states the acceptable voltage for both references.

    Setting these references beyond the published levels may damage the device, or cause unpredictable results.

    With other ADCs that have external voltage references, I have seen harmonic distortion increase as the reference threshold is exceeded, but I'm not certain as to why you would be seeing an negative sample.

    Hope this helps.

    Best Regards,

    Dan

  • Thanks Dan,

    One more question.    

    We're trying to understand how the ADC pipeline works.   We have a 20MHz clock going into the ADC (blue trace = +clk in), and the analog input (Green trace = +IN Analog).  There are both small and large dips corresponding to the rising/falling ADC clock edges respectively.  
     
     
    The smaller droop occurs 3ns after the rising clock edge and would seem to correlate with the aperture delay quoted in the datasheet of 3ns (typ).   The larger droop occurs 7.4ns after the falling clock edge, and we can't figure out what's causing this or if we should be concerned.    Both sets of droops (large and small) are 50ns apart which correlate to the 20MHz clock frequency.
     

    The edge on the analog input (green trace) occurs synchronously with the clock and is sampled repetitively.   However the edge is phase shifted in 1/32 clock UI increments, thus creating the equivalent of a sampling oscilloscope.   At 3 adjacent phase offsets, we observe a negative going excursion in the digital output that we don't see at the analog input (using a GHz scope with differential probe).
    The quantized digital signal with all phases reconstructed in the time-domain look like so:
      
    Note the negative excursion that occurs approximately 1 clock cycle prior to the large rising edge.
    We've isolated the problem to the ADS5421; however, we don't know exactly what's causing it.    We suspect that the problem lies either in the track-and-hold circuit and/or in the quantization pipeline.   Can you help us understand what occurs inside the ADC when measurements are taken and put through the pipeline?
    Many thanks in advance.
    Don