Part Number: ADS54J42
Section 8.4.2.2 of the ADS54J42 datasheet states: "There are three different test patterns available in the transport layer of the JESD204B interface. The ADS54J42 supports a clock output, encoded, and a PRBS (215 – 1) pattern. These test patterns can be enabled via an SPI register write and are located in the JESD digital page of the JESD bank." How is the clock output test pattern enabled? The datasheet does not show which register and bits to write to enable it. Thanks.
