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DAC38RF84: RF DAC resolution

F Brest
Prodigy 240 points
Part Number: DAC38RF84


Hi,

I am looking at the calculation of the SerDes lane speed.

The DAC  has a 14 bit resolutiion but the formula always make reference to 16 bits.

"FSerDes = 1 (Non-interleaved I/Q) x 368.64 Msps x 16 bits x 10/8 = 7372.8 Mbps,

where

• 10/8 is for 8b/10b decoding"

Does it mean that the number of bits sent by the FPGA is 16bits  and  it is  different from the DAC interface?

How does it work? I send 16bits and my DAC interface is 14bits so what is the purpose to do that? 16 bits as input is mandatory?

Best Regards

Fabien

  • 0
    TI__Intellectual 2750 points
    Fabien,
    It's a good question. The Sample will be N = 14 for your case, but N'+T (the encoded sample) is = 16.
    The extra 2 bits are Control bits (CS) or tail bits (T) utilized by the JESD link.

    The reason why is the JESD204B data must map into Octets (8bits) for encoding through an 8b/10b to maintain serial link transition density and common mode balance on the line.

    If you have not seen it yet, have a look at this document for an overview of the JESD2024B transport layer
    www.ti.com/.../slap161.pdf

    Regards,
    Brian