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Thanks Kevein for getting back to me. The behaviors we would like to model is an interface to an FPGA. We are using the DAC as a replacement to digital potentiometers. A TI ADC: ADC128S102 will then be used to sample the DACs outputs. A communication link, say RS422 or GigE, will be used to interface with the FPGA to extract the ADC monitor information and send it to a PC.
Usually for something like this we would refer to the Timing Requirements Table in the datasheet as this removes some of the misrepresentation you may see in simulation by not running over every operating corner, temperature, wafer lot, etc. Essentially the information in these tables are guard-banded well enough to be guaranteed behaviors and, usually, we try to provide coverage such that they can answer common questions about interfacing.
The most common timing concerns for SPI are the setup and hold time with respect to defining the critical edge, which for DAC8568 are modeled via t9 and t10 relative to the falling edge of SCLK. The device is flexible concerning clock polarity. So the SPI could be configured as CPOL = 0 with CPHA = 1 or CPOL = 1 with CPHA = 0 - though the second case needs to be mindful of t5 setup time for the first SCLK critical edge relative to the falling SYNC edge.
Is there perhaps an underlying specification outside of the Timing Requirements Table which you need answered?
Just checking in once more on this thread. Is there any way we can continue to help you with this request or have the previous responses provided what you needed?
