ADC12D1800RF: Second Nyquist image

Dan T

Part Number: ADC12D1800RF

I have a design that uses the ADC12D1800RF. We are running it in DESIQ mode, at 2.3 GSps in the second Nyquist region. I’m seeing an image across ¾*Fs.

Do you have any test data that specifies would this image should be? I'm measuring -38 dBc. Does TI believe that the ADC would cause an image here?

over 6 years ago

0 dBrock over 6 years ago

TI__Genius 12780 points

Hi Dan,

We are taking a look into your question, and will be back with you soon.

Best Regards,

Dan

0 Jim Brinkhurst1 over 6 years ago in reply to dBrock

TI__Mastermind 43870 points

Hi Dan

When operated in any of the DES modes, the ADC12D1800RF has a total of 4 interleaved sub-ADCs sampling the input signal. Due to this architecture, interleaving related spurs can occur depending on mismatch in offset, gain and sample timing in the interleaved converters.

Please review the information in this document, which describes this in significantly greater detail and has recommendations for achieving the best possible performance:

http://www.ti.com/analog/docs/litabsmultiplefilelist.tsp?literatureNumber=slaa617&docCategoryId=1&familyId=2020

There is also a TI Design which provides some recommendations regarding driving the ADC inputs for best performance in the different DES sampling modes.

http://www.ti.com/tool/TIDA-00113

I hope this is helpful.

Best regards,

Jim B

0 Dan T over 6 years ago in reply to Jim Brinkhurst1

Prodigy 235 points

The image I am seeing is much higher than the image(s) shown in the paper. Is this because I am in the second nyquist zone? Do you have any ideas as to how strong the interleaving spurs could be in the second nyquist zone?

0 Jim Brinkhurst1 over 6 years ago in reply to Dan T

TI__Mastermind 43870 points

Hi Dan

Yes, if the spurs are due to interleave timing mismatch then the spur magnitude will increase as the input signal frequency increases.

(For a fixed sample timing error a larger signal slew rate results in a larger voltage error)

To minimize the spur levels follow the mitigation techniques described in the referenced documents:

Ensure the ADC has been calibrated after being configured and with stable clock, and close to the final operating temperature. This will optimize matching of gain and offset between the interleaved banks.
Try adjusting the DTA setting (DES Mode Timing Adjust). This will fine-tune the Dual Edge sample timing between the I and Q pairs of interleaved converters. Adjust until the magnitude of the Fs/2-Fin timing spur is minimized. This may also reduce the magnitude of the Fs/4+/-Fin spurs somewhat.

I hope this is helpful.

Best regards,

Jim B

0 Dan T over 6 years ago in reply to Jim Brinkhurst1

Prodigy 235 points

I've tried moving DTA, the offset, and the FSR. None of them seem to impact the Fs/4 +/- Fin spur.

I believe that the offset and FSR are working, I'm measuring these, and I can see my DC offset and gain balance improve.

Also, tidu175a.pdf says to optimize the FSR on page 21. The data sheets says I need to re-run calibration when I change the FSR. Do I need to rerun the calibration? It doesn't seem to make a difference...

0 Dan T over 6 years ago in reply to Jim Brinkhurst1

Prodigy 235 points

I still have several images in my spectrum. I haven't been able to impact them.

0 Jim Brinkhurst1 over 6 years ago in reply to Dan T

TI__Mastermind 43870 points

Hi Dan
You are running in DESIQ mode with Fs = 2.3GSPS. What Fin are you applying?
I will try to set this up in the lab and gather some comparative data.
Best regards,
Jim B

0 Dan T over 6 years ago in reply to Jim Brinkhurst1

Prodigy 235 points

1800 MHz is a good test point.

0 Dan T over 6 years ago in reply to Dan T

Prodigy 235 points

Have you had any success trying to duplicate what I am seeing?

0 Jim Brinkhurst1 over 6 years ago in reply to Dan T

TI__Mastermind 43870 points

Hi Dan
Sorry, I haven't yet.
I tried to get it done last week but ran out of time due to other commitments. I'm traveling for a few days this week but will be back in the office on Thursday and will get the measurements done by mid-day on Thursday.
Regards,
Jim B

0 Jim Brinkhurst1 over 6 years ago in reply to Jim Brinkhurst1

TI__Mastermind 43870 points

Hi Dan

Here is some preliminary data. I am using the ADC12D1600RFRB evaluation board, with external clock at 1150 MHz, so Fs is 2300MSPS. Fin is at 1797.77MHz adjusted to around -0.5dBFS. I did a first measurement in DESI mode using a lab quality balun driving VINI only. Then I used the TC1-DESIQ-SBB to drive both VINI and VINQ and selected DESIQ mode.

/cfs-file/__key/communityserver-discussions-components-files/73/0830.ADC12D1600RF-DESxx-Spur-Evaluation-for-E2E.pdf

Fin at 1797.77MHz folds to 502.23 MHz.

The Fs/2-Fin spur shows up at 647.77MHz and is the limiting spur. After adjusting the DES Timing Adjust setting I can get this spur to around 60dB below full scale in DESI mode and around 55.6dB below full scale in DESIQ mode.

Based on this the -38 dBc spur you are getting is likely due some issue with the signal path driving the ADC inputs. If you operate in DESI or DESQ mode what does the spur performance look like? Can you share the schematic and layout for the ADC input path?

Best regards,

Jim B

0 Dan T over 6 years ago in reply to Jim Brinkhurst1

Prodigy 235 points

How would I share my schematic and layout? I'd rather not post it.
What was the spur level with DTA tuned in the worst possible manner?
When I move DTA, I don't see any change to my spur levels. The same holds for the DC and gain adjustment knobs.

0 Jim Brinkhurst1 over 6 years ago in reply to Dan T

TI__Mastermind 43870 points

Hi Dan
Thanks for the discussion off-line. Now that the DTA adjustment is working properly I think we can close this thread.
Best regards,
Jim B

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ADC12D1800RF: Second Nyquist image