ADC3222: ADC3222 layout instructions

user508578027

Part Number: ADC3222

Pls. advise what are the recommended constraints for matching of DCLK (Intra pair – between P to N, at mils) and between the DCLK to other lanes (A0,A1,B0,B1,FP).

At my design DCLK is 64MHz.

Thanks!

over 7 years ago

0 Jim Brinkhurst1 over 7 years ago

TI__Mastermind 44680 points

Hi user

You need to match the DCLK and DxN pair lengths well enough to ensure adequate setup and hold at the capture device, relative to the bit period for your operating case. With 64 MHz DDR DCLK the bit period is 7.81ns.

As a rule of thumb for that frequency I would match the pair lengths well enough to keep the pair to pair skew less than 5% of the bit period. I would match P to N well enough to make the inter-pair skew less than 1% of the bit period.

Best regards,

Jim B