Other Parts Discussed in Thread: DAC5652
Hi, TI experts.
This is the first time I use high-speed DAC, hence, I have some problems to consult you.
1. Its datasheet page5/22 gives timing diagram. It shows that (including settling time), every data converting requires around 40ns. Then, is the device's 125M SPS actually not useful?
2. The datasheet recommends WRT and CLK lines connected together. I wonder, what devices can I use to generate the 125M clock signal?
3.Datasheet pp3/22's table gives "Output Compliance Range"- -1V to 1.25V(I also see this in DAC5652's datasheet. It seems all high-speed DAC has this parameter). This means that the resistor connected to Iout and its complementary must be small enough to keep the pin's voltage below 1.25V? Does it make sense to follow the pin by an op amp to amplify this voltage?
Regards
Yatao Ling