I would like to use the ADS8354 but not at it's full throughput capability. I want to use the device in the 32-CLK, Single-SDO Mode. The datasheet timing table "32-CLK, Single-SDO Interface Specific Timing" indicates a minimum spi clock period of 41.66ns and no maximum is specified. Does the lack of a specified maximum mean I can run the SPI clock with any period greater than 41.66ns to reduce the throughput to basically any value less than 700 kSPS that I want/need?
Basically, I would like to read X samples digital from both ADC channels using a single SDO line with a 512kHz SPI clock. I realize I will not be utilizing the devices full potential of 700 kSPS with a 512kHz SPI clock. However, I'm really just interested in whether or not I can run the clock that slow and still expect the device to operate normally and deliver valid data to the SDO pin.