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ADS8354: minimum SPI clock for valid data

Part Number: ADS8354

I would like to use the ADS8354 but not at it's full throughput capability. I want to use the device in the 32-CLK, Single-SDO Mode. The datasheet timing table "32-CLK, Single-SDO Interface Specific Timing" indicates a minimum spi clock period of 41.66ns and no maximum is specified. Does the lack of a specified maximum  mean I can run the SPI clock with any period greater than 41.66ns to reduce the throughput to basically any value less than 700 kSPS that I want/need?

Basically, I would like to read X samples digital from both ADC channels using a single SDO line with a 512kHz SPI clock. I realize I will not be utilizing the devices full potential of 700 kSPS with a 512kHz SPI clock. However, I'm really just interested in whether or not I can run the clock that slow and still expect the device to operate normally and deliver valid data to the SDO pin. 

  • Hi Steven,

    Yes, the ADS8354 can support slower SCLKs than the max ~24MHz (41.66ns).  The conversions are triggered in the falling edge of CS; therefore the data rate is controlled by how fast you trigger conversion

    If you run the device with SCLK 512kHz SPI using dual SDO, in 32-clk mode, the device can support a maximum throughput of approximately ~15.5kSPS (the frame requires a minimum of 32 SCLKs falling edges).

    If you run the device with SCLK 512kHz SPI using single SDO, in 32-clk mode, the device can support a maximum throughput of approximately ~10.66kSPS (the frame requires a minimum of 48 SCLKs falling edges).

    The ADS8354 updates the SDO data on the SCLK falling edge, and reads data from the SDI bus on the SCLK falling edge; see serial interface timing and associated delays on figure 1 .

    Thanks and Regards,

    Luis