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DAC5682Z: The output of DAC5682z is strange

liu tian
Prodigy 50 points
Part Number: DAC5682Z

The output of DAC5682z is full of glitches once the devices power on. The output is as shown in the figure below.

When I give the DAC a 2.5MHz sine wave, the output of dac can probe the sine wave, however, the glitches have always existed. The output of 2.5MHz sine wave with glitches is as shown in the figure below.

zoom in



zoom in



The DAC output drive circuit is as shown in the figure below.



When I power down the amplifier, the glitches is still exist and the phenomenon is the same.I want to know if the DAC has been damaged. Is there any way to solve this problem?

  • 0
    TI__Mastermind 18065 points
    Hmmm. Your figure with the 2.5 MHz sine wave looks like there are bit errors within the MSBs; however, in the wide time sweep it looks to be localized to a specific time window. Is it possible that the pattern has been corrupted. Verify by plotting it in Matlab or equivalent. The DAC interface is a bit unclear. Vcm should be 3.3 and the load should be around 50 ohms (SE). The load resistors do not appear symmetrical and the Vcm does not appear to be the proper value. I am not aware of any time limited issue on the device that happens on first power up but does not occur again.
  • 0 in reply to RJ Hopper
    Prodigy 50 points
    I have checked the pattern. The pattern is normal. Through read the register, I found the fifo error is assert. When i clear the fifo error，the fifo error return to assert. In addition, the toggle frequency of fifo error is the same with the frequency of glitches. The frequency of clkin and dclk are 400MHz and 200MHz respectively in 1XDAC non-interpolation mode . The dll is locked. The frequency of glitches is about 120Hz. When i change the frequency of clkin and dclk to 20MHz and 10MHz respectively. The frequency of glitches becomes 6Hz. I have tried the sw sync and direct sync. The results is the same. How can i clear the fifo error or what caused the fifo error?
  • 0 in reply to liu tian
    TI__Genius 9695 points
    Hi Tian,

    Please verify clkdiv_sync_dis and fifo_sync_dis bits are set to prevent continuous syncing of the clock dividers and FIFO.

    Thanks,
    Eben.