Other Parts Discussed in Thread: LMX2594, , ADC12DJ3200
Hi,
I am trying to link ADC12J4000 to xilinx xc7vx690t by xilinx jesd204b ip core on my board, we are using lmx2594 so the sampling clock could up to 4GHz, we are going to set ADC at mode 'decimation = 1'(the 1st mode of datasheet table 11). but to be honest, some jesd204b link parameter are ambiguously for me. thanks for your explaining my question:
Q1, just check, for my use case, i suppose all the 204b control register could be default value.
Q2, for single ADC, how should i understand 'M'=8 since from 204b standard, M is defined as 'the number of converters per device', I suppose M should always be '1' for ADC12J4000?
Q3, i could get 256bit@200MHz parallel data core output data and how should I deframe these bits into sample data according to table 12& table 13 since there are in total 512 bits in these 2 table?