This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADC12J4000: jesd204b parameter and output data

Part Number: ADC12J4000
Other Parts Discussed in Thread: LMX2594, , ADC12DJ3200


I am trying to link ADC12J4000 to xilinx xc7vx690t by xilinx jesd204b ip core on my board, we are using lmx2594 so the sampling clock could up to 4GHz, we are going to set ADC at mode 'decimation = 1'(the 1st mode of datasheet table 11). but to be honest, some jesd204b link parameter are ambiguously for me. thanks for your explaining my question:

Q1, just check, for my use case, i suppose all the 204b control register could be default value.  

Q2, for single ADC, how should i understand 'M'=8 since from 204b standard, M is defined as 'the number of converters per device', I suppose M should always be '1' for ADC12J4000?  

Q3, i could get 256bit@200MHz  parallel data core output data and how should I deframe these bits into sample data according to table 12& table 13 since there are in total 512 bits in these 2 table?

  • Hello User,
    I would definitely recommend utilizing the TSW14J57 evaluation platform to get started if there is some question about configuration of the JESD core and clocking. You will be able to use the ADC GUI and HSDC Pro software to get the system up and running at the rate you want with less hassle, and we will be able to support your evaluation more directly.

    We also have a 'bridge' TSW card and Xilinx firmware reference designs avaliable with the TSW14J10. The TSW14J10 spans between the ADC12J4000 board and the Xilinx board allowing use of HSDC Pro software tool. The closest build we have is for a VC707, but I think you would be able to port it to the VC709 (I am guessing that is what you have).

    For the rest of your questions I have sent this post to an engineer that works with the ADC12J4000.

  • User, my colleague pointed out a mistake to me. The VC709 has different transceivers than the VC707 (GTX vs GTH). Therefore our reference design will not simply recompile for the VC709. The GTH is supported by the JESD204B PHY IP so it should be able to be ported with some effort.

  • thanks for your quick response. actually now I can make the jesd link up and running at user data state. but I am struggling to deframe the transport layer data as my Q3 stated, how should I mapping the 256bits parallel data from Xilinx ip core to each sample point(12bit) as datasheet table 12& table 13.
  • Hi user

    You will need to do you mapping on 2x 256 bits since the total frame size requires 512 bits as you have noted.

    We have a firmware reference design for a similar product, the ADC12DJ3200 and the Xilinx KCU105 available here:

    Given the similar 12-bit data formatting of the ADC12DJ3200 I think it is worth reviewing the mapping method used in that firmware.

    Tables 12 and 13 in the datasheet show different viewpoints of the same information. Table 12 shows the M=8 formatting that we used to comply with the JESD204B requirements while providing minimum latency and implementation complexity of the ADC. Essentially we broke up the single ADC data into 8 interleaved sub-ADCs so that the data from each sub-ADC could be placed into a corresponding lane for that ADC. Table 13 shows the same data, but how the samples are ordered for the single ADC usage. This topic has been previously discussed in much more detail in an earlier E2E post here:

    I hope this is helpful.

    Best regards,

    Jim B