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ADC12J4000: About ADC Test Pattern

Part Number: ADC12J4000
Other Parts Discussed in Thread: TEST,


Customer is using ADC12J4000EVM, then I have a question about ADC Test Pattern. The ADC sent the ADC Test Pattern, however, the FPGA received the different data as follows. Please let me know the root cause of this issue.

transmitted data *ADC Test Pattern

FPGA received data

 Best Regards,


  • Hello Toshiyuki,
    I have sent this over to an engineer that works with the ADC12J4000
  • Hi Toshiyuki

    The highlighted values are definitely incorrect. 

    What FPGA platform is the customer using to capture the ADC data?

    Does the customer see the same incorrect values in every frame, or are the values not consistent from frame to frame.

    Can they try reducing the ADC clock rate to see if the errors are the same at lower serial line rate?

    Can they try increasing or decreasing the serializer pre-emphasis to see if that changes the behavior?

    Best regards,

    Jim B