LM15851: the LM15851 inputs protection

Hi Vic
100 ohm resistance in series with the FPGA logic outputs should be sufficient to limit over-driving the LM15851 logic inputs in the case where the FPGA powers up first. You might also want to check when the FPGA actually gets configured. Usually the FPGA outputs will be either high impedance or weak pull-up or pull-down until the device is configured. If FPGA configuration happens after the LM15851 is powered up then you may not need to add any series resistors.
Best regards,
Jim B

Hi Vic

Regarding your latest comments and questions:

"As I understand it, when current is injected into an input, it forward biases the protection diode. The voltage developing on the diode is not harmful as long as the current stays in the Absolute Maximum Ratings, and I shouldn't care about the developing voltage."

Merely limiting the driving current to +/- 25mA does not ensure that the voltage at the pin stays within the allowable range. It is quite likely that +/-25mA applied to an input pin could force the voltage outside the allowed range. The voltage at the pin is dependent on the characteristic of the ESD diode and other internal circuitry.

"Similarly, when a voltage is applying on an input in excess of supply, then current flows through the diode. The current  is not harmful, as long as the voltage stays in the Absolute Maximum Ratings."

Limiting the voltage to the allowed range should also limit the current flowing into or out of the input pin. This is true for pins that have traditional ESD diode connections to supply and/or GND.

"So, I should care about only one thing of the two: current or voltage. The other will be met naturally.

Is my understanding correct?"

As described above this is not necessarily correct. 

I hope this is helpful.

Best regards,

Jim B

Hi Vic

In general for semiconductor products the datasheet input current AND input voltage limits must always be followed.

We include both input voltage and input current limits because for some devices with some input structures current might be exceeded first, and for others the voltage might be exceeded first. For the LVCMOS inputs of this specific device following the voltage limits will also minimize the input current. This is not always the case for all inputs on all devices.

Best regards,

Jim B

Hi Vic
For the 100 ohm value I did a simple calculation just considering the maximum allowed current per pin. Assuming a 1.8V FPGA source voltage driving into low voltage (0V for ease of calculation) the maximum current would be 18 mA. It would actually be somewhat lower due to the voltage drop in the ESD diode for the pin. 100 ohms in series is low enough resistance that it should not cause problems with normal operation of the logic I/O function, rise/fall time, etc.
However since the ADC input pins also have voltage limits, and this condition could still exceed the positive voltage limit of V(VA19)+0.15V, I highly recommend that the FPGA logic outputs not be configured and enabled until after the LM15851 is powered up, and are disabled before the LM15851 is powered down.
Best regards,
Jim B