Hello
As i decide to capture converter data with xilinx spartan 6 family for initial tests, i wonder is it possible to clock the converter with lvds clock outputs of sp6 family?
I searched and found some contradictory information regarding the possibility of this connection and it's configuration type (termination resistors, etc.).
In AN1318 of STMicroelectronics titling "INTERFACING BETWEEN LVDS AND HIGH SPEED DIFFERENTIAL LOGIC FAMILIES", it is mentioned that:
these statements seem to be in contradiction.