ADS42JB46: ADS42JB46 EVM and Datasheet Questions!

BobL

Part Number: ADS42JB46

1) Looking at the ADS42JBXXEVM-SCH, why is the SYSREF driven LVPECL, while the CLKIN is driven LVDS?

2) Per the datasheet page 10, the JESD204B Digital Outputs are supposed to be externally terminated with 50 ohms to IOVDD. None are show in the EVM schematic.

(DIGITAL OUTPUTS (JESD204B Interface: DA[0,1], DB[0,1])(2)), (2) 50-Ω, single-ended, external termination to IOVDD.

Thanks in advance!

over 6 years ago

0 BobL over 6 years ago

Intellectual 330 points

Answered #2 myself, terminations are in the FPGA CML receiver. Likewise, for the JESD204B DACs the terminations are in the DAC.

0 jim s over 6 years ago in reply to BobL

TI__Guru* 91947 points

Bob,

Both are actually driven as LVPECL. The termination for the SYSREF is slightly different to adjust the common mode to meet the spec of the part and to DC couple this input as SYSREF is normally turned off after the link has been established.

Regards,

Jim

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ADS42JB46: ADS42JB46 EVM and Datasheet Questions!