This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS1226: Follow-up to ADS1226 stuck at the power-up

Part Number: ADS1226
Other Parts Discussed in Thread: ADS1225, ADS1220

Hello TI engineers and all others,

I have some follow up questions to issue of incorrect operation of the ADS1225/ADS1226 when repeatedly powered-up as stated in this previous forum posts (link1, link2).

We encounter the issue, that the conversion times are higher than stated in the datasheet with max. 13.3ms (measured up to 14.6ms) with some fluctuations at the beginning when repeatedly powered-up. This leaves us with permanent incorrect measurements when this issue appeared after power-up (START pin is not permanent high, see InitFailure.PNG and InitSuccess.PNG). It is not repeatable on all boards; on other boards between 10 and 100 repeated powers-up are necessary until this issue appears.

As it is stated in these forum posts, there might be an unwanted charge left in the POR circuitry when repeatedly powered-up (and I guess this causes the internal oscillator to run incorrectly) resulting in this issue. We put a 1k bleeding resistor on DVDD, which resulted in reaching 0V after ca. 500ms (see 3V3VDD_Shutdown_1k_Pulldown.png). Unfortunately, this did not improve the appearance of this issue. Same is true for also putting a pull-down resistor on AVDD.

Now I have some follow-up questions:

  1. Is the unwanted charge drained away fully with such a pull-down resistor on DVDD when 0V is reached (or is this charge between some other pins)? Do you have some specifications on that?
  2. We could encounter some voltage dips in our application due to net instability. Can this issue also happen after only one incorrect re-powering (DVDD not returned to 0V)? Do you have any data on that or a systematic behavior you can provide?
  3. Does this incorrect power-up only result in a slightly slower oscillator, so one can measure the conversion time at the beginning and it will stay true for the whole operation?

Schematic: We use a 3.3V LDO on AVDD and a 3.3V switching regulator on DVDD, which powers up cleanly 60ms after AVDD. AVDD and the reference voltage powers-up simultaneously. Buffer is not enabled and high-speed mode is selected.

Thanks in advance,

Benjamin

InitSuccess.PNG


InitFailure.PNG



3V3VDD_Shutdown_1k_Pulldown.png (yellow line with 1k pull-down)

  • Benjamin,


    I'm sorry that you're having problems with the ADS1226. Do you have a schematic and layout that you are able to share? It might help with debugging this supply reset problem.

    1. The pull-down resistor is meant to pull out the charge on the decoupling capacitor for any supply pin. This would be for AVDD and DVDD. However any residual charge anywhere on the device could make it's way internally to the supply and cause problems in completely discharging the supply. That's why it's important to discharge any pin connections, including analog inputs and digital pins.

    We don't have any specifications on the issue. This problem is often dependent on supplies and signals driving this device. Supply decoupling capacitance often will have a large role in finding this issue. If the supply restart is very short, then it might help to increase the decoupling capacitor to provide charge through the low-supply event. If the supply restart is longer, using a smaller decoupling capacitor may help by allowing the supply to drop to 0V faster. Adding a pull-down resistor is meant to help this type of event.

    In my experience, the problem is more related to connections to the AVDD supply than the DVDD supply. However, it is likely an effect related to both supplies. If you haven't already, try changing supply decoupling capacitance size.

    2. This issue could happen on a single restart of the device. It really depends on the residual charge on the capacitance in the POR circuit. Because this is a function of supply sourcing, decoupling capacitance, start and power down times, supply voltages, and available supply current, it's hard to find a definitive solution.

    3. The incorrect power-up causes problems with the initial setup in the device. This includes the decimation ratio (for this delta sigma ADC) and the oscillator frequency settings internal to this device, both will have an effect on the ADC output data rate. There are also settings available for setting the output bits in the device (as in 12- and 16- bit output formats), but I believe that is also combined with the decimation ratio. However, the output data rate may be a good outwardly visible indication that the device has powered up to the correct state.

    Again, if you have a schematic and layout, I'd be interested in looking at it for different possible solutions. As I mentioned in a previous post, our newer devices have better power-on-reset circuits that would do a better job with repeated power-ups. The ADS1220 is similar to the ADS1226 and has a better power-on reset circuit. However, if you already have boards, I don't think it's worth changing the device out.


    Joseph Wu
  • Benjamin,


    I had one other question that I forgot to ask. What are you showing with the oscilloscope photo? I assume one is the supply voltage (presumably at the AVDD pin of the device), but what it the other trace?


    Joseph Wu
  • Hi Joseph,

    thanks for you detailed and fast reply. The other trace on the oscilloscope image shows the reference trace without the 1k pull down resistor on DVDD for comparison.

    Attached you'll find snippets of the relevant schematic and layout parts. The added oscolliscope shows the voltage power-up of 2.048 reference voltage (CH1), AVDD (CH2) and DVDD (CH3).

    We plan endurance testing (no. failures / power-ups) to get some quantitive data the next days to compare this assembly values with these possible improvements: 1k pull down resistor on DVDD, AVDD and reduced decoupling capacitance 10µf/1µf). I'll get back to you end of week.

    BR Benjamin

  • Hi Joseph,

    I've got a quite interesting development.. We were preparing for the endurance test (controlled re-powering to quantify the frequency of occurrence of this issue) and used a different initialization sequence. During our investigation we tried different initialization sequences (calibration, 25th clock before beginning of operation, etc..), but found out that with an initial calibration the issue still appeared and left it out. We do not need the calibration of the ADC for accuracy.

    Now with this new sequence the issue did not appear any more (4000 automated tries on one board). On board with the same setup, the issue appears every 20-60 power-ups with the old sequence, but not once with the new sequence.

    How do you explain that with the POR circuitry? Is the capacitance somehow drained away at the beginning when permanent conversion is activated at the beginning?

    We have a hard time to continue investigating this and we would appreciate you looking a bit more into that and maybe explaining this reproducible behavior. Is this new sequence permanently resolving this issue? Thanks!

    Old beginning sequence direct start of conversion: Issue often reproducible on multiple boards

    New sequence with calibration and short period of permanent conversion: Issue not any more reproducible

  • Martin,


    Just to be sure that I understand, by adding an initial calibration, the problem goes away? I don't know why that would be any different. The calibration ensures that the internal calibration registers are set correctly. This would include an offset calibration register and a gain calibration register to make sure the reference and input sampling capacitances are calibrated.

    However, these calibration registers only affect the calibration, they won't change the configuration of the ADC that is normally set at power up. I would be skeptical and make sure that the power-down and power-up are the same for both the old and new sequences. Are there any other changes to the schematic or power-down/power-up sequences?

    Now that I've seen the schematic, I would like to make a couple of suggestions. First, I would remove all the 10uF capacitors to start. That amount of capacitance stores a lot of charge and removing them would reduce the residual charge during power-down. This would be C9 and C7 associated with the reference voltage. Besides, the MAX6126 has a maximum cap load of 10uF for stability, and you're right on the edge. I would also remove C2 to start the testing. All of these capacitances can be added back in, but start with the minimal 100nF caps for decoupling and reference load.

    I would also replace FB1 with a short. Generally, I don't like to use inductive filters on the supply. Because the ADC has digital currents (and some digital currents for sampling in the analog supply as well), the spiked current can cause spikes in the voltage with an inductor because of the high LdI/dt. Most ferrites are pretty small, but larger inductors can really disrupt supplies.


    Joseph Wu
  • Hi Joseph,

    Thanks for your input regarding dimensioning. It's not only the calibration, but the short period of time permanent conversion (START pin tied high) afterwards. Yes, the hardware setup (capacitance values, ferrite beads) was the same and as shown in the schematic above for the working and repeatable not working initial sequence. I tried the suggestions you made (C2, C7, C9 removed) with both sequences (see above) and it did not make any difference. This means: no improvement with the first initial sequence (issue still appeared repeatedly) and no appearance with the new initial sequence.

    Now, I have this reproducible behavior with these 2 start-up sequences, which is not dependent on the capacitance values and which I cannot explain with the POR reset issue you decribed. It's kind of frustrating now and the other posts didn't end in resolving this issue either.

    Can you please investigate this and tell me, if this resolves this issue permanently?
    Should we use ADS1220 in future when we can encounter a single short re-powering of our device? Thanks.

    BR Benjamin
  • Benjamin,

    In my experience with this device, it has been the sizing of the capacitance and how fast these decoupling capacitances are discharged that allow for device to start up correctly once power is restored. I'm still surprised that changing the capacitances doesn't have any affect at all. With your change in sequence, it's possible that there is more current drawn on with the START pin initially high.

    I can help in this investigation, but I'm not sure how to verify this problem and duplicate it. I can get my own board and see if I can power up the device in a similar manner, but I'm not sure if I have a reliable control to power up the device in any particular sequence. Additionally, I'll need your exact sequence and timing. I'm still a bit unclear as to when the power is turned on and how long the START is held before you run the calibration, and then how long you continue the conversion before you begin pulsing the START pin to acquire real data.

    I'm also a bit unsure how the good power up sequence differs from the first failed sequence you show in your post. For the good power up sequence, you start with a calibration, a set of conversions, and then begin pulsing the START pin after a short delay:

    For the first failed sequence you've shown, you have the same calibration, a set of conversions and then begin pulsing the START pin:

    There isn't a delay, but by this time, the device should have already come up to a stable state. However, there isn't a /DRDY indication going low, even though the conversion time shown in the previous set of conversions should have shown the conversion to have completed (based on the alignment of the START pulses and the following SCLK pulses.

    The one other thing different about the first failed sequence is that there is a wide initial /DRDY pulse. This might indicate when the power supply first started up, but I found it unusual that the /DRDY powered up in the high state.

    As I mentioned earlier, I may be able to duplicate the problem, but I'll need as much information about how this board is constructed. The problems that you see are not digital problems but rather involve some sort of analog settling within the digital section.

    On another note, I would consider the ADS1220 as the next generation device to the ADS1226 and it does have better specifications. I also know that it has a more reliable POR setup than the ADS1226. The POR circuitry was designed for different power-sequencing conditions including brownouts as well as standard power-up. It was tested more completely based on what we had learned from the other devices in the product line. However, it still has power supply recommendations to prevent the digital from coming up in an unknown state. Regardless, for all those reasons, I would use the ADS1220 over the ADS1226.

    Joseph Wu