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DAC34H84: DAC34H84

Eric Cui13
Intellectual 920 points
Part Number: DAC34H84

hi,

I want to use the DAC34H84 to output a sine wave.The input is a 20MHz sine wave and the output is this sine wave.

How should I configure this chip's register?

Thank you.

  • 0
    TI__Guru 73389 points
    Hello Eric,

    The DAC34H84 has many features such as interpolation filters and NCOs. The configuration of the chip's register highly depends on your system requirement. You will first need to figure out the effective data rate of your waveform. Your sine wave is at 20MHz, but what is the sample rate of the data (i.e. the entire FFT BW). This will then determine the interpolation factor (if you do want to use it) and the final DAC update rate.

    you may refer to some forum posts on the configuration of the DAC34H84. One example is shown below:
    e2e.ti.com/.../687857

    Some basic DAC tutorial:
    www.ti.com/.../slaa523a.pdf


    -Kang
  • 0 in reply to Kang Hsia
    Intellectual 920 points
    hi,

    1. I configured this chip in the order of Table 10 in the manual on P58. However, when reading the 0x05 register, the first read is 3e58, and the second read is 3e78. Is there a problem with the configuration?
    2. According to what order to configure the chip?
    3. I don't enable fifo, input 5MHz sine wave, interpolation is X8, need nco, mixing. However, the frequency spectrum analyzer was found to be incorrect.
    4. Also, the usage of the DAC3484EVM Software Control software is a little blurry. Hope can help.

    Thank you.
  • 0 in reply to Eric Cui13
    TI__Guru 73389 points
    Hi Eric,

    1. these are the alarm registers indicating the errors. You will need to narrow down the source of error before proceeding. Chances are the sequencing of the FPGA + DAC programming need to be fine tuned. You may check out the app note below for detail:
    www.ti.com/.../slaa584.pdf
    2. You can refer to the app note above.
    Both 3 and 4 require more information for me to help out. Please list out the exact procedures and also the observations for us to pin point some recommendations. By the way, with the interpolation enabled, TI highly recommend the usage of FIFO. Most likely the alarms that you are seeing in 1) is due to the FIFO not being there to absorb the latency difference between the FPGA and DAC.
    -Kang
  • 0 in reply to Kang Hsia
    Intellectual 920 points

    hi，

    I now input a sine wave, 20MHz. If I do not mix and so on. The output should also be sinusoidal. But now it is found that the output is clutter.

    After I finished writing all the registers, when I read the registers, I found that one of the two registers was problematic.

    Part of the schematic.pdf

    Configured registers.txt
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    The first 24 bits are written to the register, the highest 8 bits are the address bits, and the lower 16 bits are the register values.
    The right arrow indicates that after reading all the registers, the value read from the register is read.
    Register address 0x04, 0x05 value is not the same.
    I only do a simple sine wave output, no mixing,
    FIFO and PLL are not enabled.
    spi_wr_data[0] <= 24'h02F002;---->F002
    spi_wr_data[1] <= 24'h02F002;---->F002
    spi_wr_data[2] <= 24'h00041C;---->041C
    spi_wr_data[3] <= 24'h01050E;---->050E
    spi_wr_data[4] <= 24'h040000;---->BFFF-------
    spi_wr_data[5] <= 24'h1B0800;---->0800
    spi_wr_data[6] <= 24'h07FFFF;---->FFFF
    spi_wr_data[7] <= 24'h0C0400;---->0400
    spi_wr_data[8] <= 24'h0D0400;---->0400
    spi_wr_data[9] <= 24'h0E0400;---->0400
    spi_wr_data[10] <= 24'h0F0400;---->0400
    spi_wr_data[11] <= 24'h140000;---->0000
    spi_wr_data[12] <= 24'h150000;---->0000
    spi_wr_data[13] <= 24'h160000;---->0000
    spi_wr_data[14] <= 24'h170000;---->0000
    spi_wr_data[15] <= 24'h18280F;---->280F
    spi_wr_data[16] <= 24'h190840;---->0840
    spi_wr_data[17] <= 24'h1A0030;---->0030
    spi_wr_data[18] <= 24'h1E1111;---->1111
    spi_wr_data[19] <= 24'h1F1182;---->1182
    spi_wr_data[20] <= 24'h202400;---->2400
    spi_wr_data[21] <= 24'h221B1F;---->1B1F
    spi_wr_data[22] <= 24'h2307FF;---->07FF
    spi_wr_data[23] <= 24'h240000;---->0000
    spi_wr_data[24] <= 24'h2D0004;---->0004
    spi_wr_data[25] <= 24'h2E0000;---->0000
    spi_wr_data[26] <= 24'h2F0000;---->0000
    spi_wr_data[27] <= 24'h03F001;---->F001
    spi_wr_data[28] <= 24'h03F001;---->F001
    spi_wr_data[29] <= 24'h050000;---->3D78------
    spi_wr_data[30] <= 24'h050000;---->
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

  • 0 in reply to Eric Cui13
    TI__Guru 73389 points
    Eric,
    please advise and describe the symptom of the output.
    I see FIFO again is not enabled even though I had advised to do so. Please try to set the configuration to have the FIFO enabled and try again.

    -Kang