Part Number: ADS54J42
Hi,
We are using an ADS54J42 to sample a DC coupled signal coming from an optical Analog Front-End. The AFE needs to be DC coupled and to use all 14 bits we need the input to be biased at -0.95VDC differentially at zero light input. The sampling speed is 400MHz with 100MHz base clock. The problem lies in that if we bias the ADC input to -0.95V diff we can see a quite strong leak-through of the 100MHz base clock in the sampled data (FFT). This leak through is somewhere around -40dB below full scale and it dissappears completely if whe have 0VDC bias.
The question is: Can we use the ADC in this way or does the signal fed to the ADC input, even if it is DC coupled, have to be symmetrically swinging around 0V?
Best Regards
Jens Rasmussen
