ADS8328: Reading CFR and data.

Hi Oleg,

Welcome to our e2e Forum! Why is it that you have to perform a bit shift to read the ADS8328 CFR or Data? That should not be necessary if you are using the correct SPI CPOL and CPHA configuration. Do you have screen captures to share with us showing your interface setup?

Hi Tom.
1. I write to the following configuration the CFR = 0x06FF and read back 0x0DFE, so as to correctly interpret, I have to perform right shift by 1 bit.
2. Then I read data, I check the TAG bit that is 16 th SCLK but is not 17th SCLK and I need perform right shift data as a result format of data are 15 bits.
3. The SPI Interface is share with another device the ADS1220 , the interface operates in SPI mode 1 where CPOL = 0 and CPHA = 1.
4. Unfortunately I do not have screen captures.

Best regards
Oleg

Hi Oleg,

If you are missing the MSB, chance are you are violating one of the timing specs, like perhaps the tSU(CSF-SDOVALID).  Getting some screen captures of your CFR write and read sequence would be really helpful here in trying to determine what might be going wrong.

Hi Tom.
I send screen capture ,following signals CS, SDI ,SDO of interface SPI .
I hope that help to understanding the problem.
Best regards
Oleg

CAPTURE_ADS8328.pdf

Hi Oleg,

Sorry for the delay in getting back to you and thank you very much for the screen shots! Can you speed up your SCLK any and/or send 24 clocks to the device while /CS is low (send an extra 8 clocks by writing 0x00 to your SPI transmiter)? Can you also try writing the reset command and then immediately read back the CFR (write 0xF000 to reset)?

How are you progressing here Oleg?

Hi Tom.
To follow the your of advice , I speed up SCLK up to 20Mhz and sent an extra 8 clocks by writing 0x00 in SPI transmiter , also wrote the reset command and have read back the CFR .
But unfortunately I don't get any of change.

Best regards
Oleg

Hi Oleg,

Can you provide a screen capture of that setup?