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ADC08DJ3200: Number of JESD204B lanes required for 5 Gsps

Part Number: ADC08DJ3200

Hello,

I'm considering using [ADC 08 DJ 3200] with 5 Gsps (Single-Channel Mode).

I want to minimize the GTX of the FPGA to be used,
Can it be changed by register setting of the device?

Or may it need all of DA 0 - 7 & DB 0 - 7 (total 16)?

Best regards,

Abei.

  • Hi Abei

    Please refer to Table 10 in the ADC08DJ3200 datasheet.

    In single-channel mode there are 3 possibilities. The one with the fewest number of lanes is JMODE = 4. This will have a total of 4 JESD204B data lanes, 

    For a sample rate of 5 GSPS the ADC samples on both rising and falling edges of CLK, so Fclk = 2500 MHz. 

    Since R = 5, the serial bit rate will be 2500 MHz * 5 = 12.5 Gbps.

    The next wider interface JMODE = 5 uses 8 lanes. For this mode of operation the bit rate will be half the speed, or 2500 * 2.5 = 6.25 Gbps.

    There is a 16 lane mode as well, with JMODE = 17. In this mode the interface rate will be 3.125 Gbps.

    I hope this is helpful.

    Best regards,

    Jim B

  • Hi Jim B

    Thank you for your kind & quiq response.
    I understood the relationship between JESD204B setting and data rate.

    Best regards,

    Jim B