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AMC1305M25: question for e/c table

Part Number: AMC1305M25

Customer would like to know how much tD timming when tCLK = 50nS regarding to the 8.12 table in the d/s. Thanks.  

Regards,

Brian

  • Hi Brian,

    I believe you are referring to section 7.11 - Switching Characteristics on pg. 12 of the AMC1305M25 datasheet. the delay time (tD) is the time it takes for the data output (DOUT) to change to the next valid state after a falling clock edge. That is the 15ns MAX time shown in the datasheet. With a clock cycle time of 50ns, that gives you 10ns setup time to read valid data on the rising clock edge. Hold time would be 25ns minimum, 40ns maximum (assuming 50/50 duty cycle).