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ADS4222: which clock buffer to work with?

Part Number: ADS4222
Other Parts Discussed in Thread: CDCLVD2102, CDCLVD1213, CDCLVD1204

Hi Team,

From our ADS4222 datasheet, 

Customer is looking for a clock buffer to work with it. They will operate this device at highest sampling rate.

I have 3 quick questions:

(1) the recommend input clock amplitude for LVDS is 0.7Vpp, LVPECL is 1.6Vpp. what does this meant? differential typical voltage?

(2)  what is VODH and VODL logic for this ADC? where to find it, thanks.

(3) Is CDCLVD1204, CDCLVD1213 and CDCLVD2102 all suitable to drive?

Thanks.

Andrew

  • Andrew,

    (1) the recommend input clock amplitude for LVDS is 0.7Vpp, LVPECL is 1.6Vpp. what does this meant? differential typical voltage?

    This is the differential swing about the common mode of the signal when using that standard.

    (2)  what is VODH and VODL logic for this ADC? where to find it, thanks.

    This can be found on page 10. VHL = DRVDD - 0.1V (Min)   and  DRVDD (TYP).      VLO = 0V (TYP)  and 0.1V (Max)

    (3) Is CDCLVD1204CDCLVD1213 and CDCLVD2102 all suitable to drive?

    Yes. Follow the termination example shown in Figure 161 if you are driving the input clock from an LVDS source, like the CDCLVD1204. 

    Regards,

    Jim

  • Jim thank you for fast response!
    For (1) where I don't understand is, CDCLVD1204 for example, the LVDS VOD (Differential output voltage magnitude) max is 450mV, min is 250mV. How to link with ADS4222 clock input range for LVDS, thank you!!

    Andrew
  • Andrew,

    The typical swing for each leg of an LVDS output is 350mV. You will notice that the CDCLVD1204 spec is centered about this (250mV - 450mV). On the ADC data sheet, the input typical value is specified after this signal is received, which is 350mV + 350mV = 700mV  typical input.

    Regards,

    Jim

  • Thanks Jim, You are the man!