I am trying to achieve multichip synchronization with two ADC12J4000.
I am using an Arria10 with the Altera JESD IP as JESD Receiver (subclass 1).
My clock configuration is ADC CLK = 3932.16 MHz (Decimation=8) and the SYSREF = 0.640 MHz (Continuous sysref).
The SYSREF is generated by the same device for the 4 jesd devices (2 ADCs + 2 Altera IP)
Both ADCs can detect the SYSREF, the sysref bit "detect" is at 1, and not marked as dirty, the bit "aligned" is also at 1.
However my multichip synchronization appear to not work as I see a delay of a few samples between both ADCs (0 to 30).
(To measure that, I send the same signal to both ADCs (noise) then I do a cross-correlation of the signal samples by the ADC.)
Also this delay changes after powering off/powering on the ADCs.
What could be the cause of this ?
Is there a procedure to achieve multichip synchronization ?