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ADC12J4000: Multichip synchronization

Part Number: ADC12J4000


I am trying to achieve multichip synchronization with two ADC12J4000.
I am using an Arria10 with the Altera JESD IP as JESD Receiver (subclass 1).
My clock configuration is ADC CLK = 3932.16 MHz (Decimation=8) and the SYSREF = 0.640 MHz (Continuous sysref).
The SYSREF is generated by the same device for the 4 jesd devices (2 ADCs + 2 Altera IP)

Both ADCs can detect the SYSREF, the sysref bit "detect" is at 1, and not marked as dirty, the bit "aligned" is also at 1.
However my multichip synchronization appear to not work as I see a delay of a few samples between both ADCs (0 to 30).
(To measure that, I send the same signal to both ADCs (noise) then I do a cross-correlation of the signal samples by the ADC.)
Also this delay changes after powering off/powering on the ADCs.

What could be the cause of this ?
Is there a procedure to achieve multichip synchronization ?

  • Hi,

    We are looking at your question and will get back to you soon.



  • Hi Avantx

    It sounds like you are doing most of the things necessary to ensure alignment. There may be one additional detail that is required.

    When using decimation mode, the NCO phase between the 2 ADCs must also be synchronized. This is discussed in Multiple ADC Synchronization in the ADC12J4000 datasheet. The NCO phase accumulators are reset at the completion of the ILA phase of link startup. This means that for the ADCs to be synchronized both links must be enabled in the same LMFC period. In other words the ~SYNC de-assertion from FPGA to both ADCs must happen in the same LMFC period. You may need to add ~SYNC combining logic in between the two Altera JESD204B Receive IP blocks, so that ~SYNC to both ADCs are de-asserted simultaneously.

    If you are already doing that, and still having issues with synchronization please let us know and we'll help to debug further.

    Best regards,

    Jim B

  • Thanks for your answer.
    I didn't say it, but indeed I am already ANDing the SYNC signals.

    Would it work better with a single pulse as a SYSREF (and not a periodic SYSREF) ?

  • Hi Avantx

    It shouldn't matter whether SYSREF is pulse, burst or continuous as long as it is the correct frequency for the ADC mode, clock frequency and K value.

    Your mode is Decimate by 8.

    Is P54=1 or 0?

    Is DDR=1 or 0?

    How many lanes of data are active?

    What is the K or KM1 value you are programming?

    With that information and the input clock frequency of 3932.16MHz I can confirm the proper LMFC and SYSREF frequency.

    Best regards,

    Jim B

  • Hi,

    I am using the configuration from Table17 on the datasheet:

    Decimation 8
    DDR 0
    P54 1
    L 4

    K 24


  • Hi Avantx
    For those settings and your applied clock frequency of F_DEVCLK = 3932.16 MHz, the maximum possible SYSREF frequency is:
    F_LMFC = F_BIT / (F * K * 10) = 3932.15*1.25 / (2 * 24 * 10) = 10.24 MHz. Your SYSREF of 0.64 MHz is 10.24/16, which meets the requirements for SYSREF being a sub-harmonic of F_LMFC.
    You just need to be sure the SYSREF signal applied to the ADC meets the amplitude and common mode voltage requirements listed in the datasheet.
    Best regards,
    Jim B
  • Thanks for your answer. I think I am correct with the SYSREFvoltage/amplitude requirements.

    When does the SYSREF must be started ?

    Currently, I start SYSREF before powering up both ADC, but after FPGA loading is this correct?


  • Hi Avantx

    Here is the recommended startup sequence.

    1. Power up or reset the ADC12J4000 device.
    2. Power up and configure DEVCLK and SYSREF clock sources
    3. Program JESD_EN = 0 to shut down the link and enable configuration changes.
    4. Program DECIMATE, SCRAM_EN, KM1 and DDR to the desired settings.
    5. Configure the device calibration settings as desired.
    6. Program JESD_EN = 1 to enable the link.
    7. Initiate a calibration (set CAL_SFT = 1).
    8. Apply at least one SYSREF rising edge to establish the LMFC phase. (assumes SYSREF delay RDEL has already been configured properly for clean SYSREF capture)
    9. Configure FPGA JESD204B data receiver
    10. Assert SYNC~ from the data receiver to initiate link communications.
    11. After the JESD204B receiver has established code group synchronization, SYNC~ is de-asserted and the ILA process begins.
    12. Immediately following the end of the ILA sequence normal data output begins.

    Best regards,

    Jim B

  • Hi,

    I ended up with adding a software programmable delay into my fpga design.
    I think it could help developpers if in future DACs/ADCs you add a way to measure delay between multiple devices (or at least a way to tell if devices are synchronized or not)

    Thanks for your help.

  • Hi Avantx

    As long as the following criteria are met the phase alignment of captured input signals should be consistent:

    1. All ADCs have consistent NCO frequency/phase settings
    2. SYSREF is properly captured at each ADC and the FPGA on a consistent CLK edge
    3. ~SYNC de-assertion is captured by all ADCs in the same LMFC period (this is required to give aligned NCO frequency/phase results)
    4. Elastic buffers in JESD204B receive IP blocks consistently release data on same LMFC boundary

    If you see a variable phase offset from startup to startup between ADC data streams then one of these requirements is not being met. It should not be necessary to compensate for a different phase offset each time the system is started.

    A small consistent phase offset can be possible due to the differences in aperture delay from ADC to ADC. Typical aperture delay for the ADC12J4000 is approximately 0.64ns. Part to part variation will result in small differences in this value for each converter, but the difference will be consistent for each device given consistent supply voltage and operating temperature.

    I hope this is helpful.

    Best regards,

    Jim B