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ADC3222: ADC3222

serkan unal
Prodigy 160 points
Part Number: ADC3222

In its datasheet there writes 0.7 Vpp nominal for LVDS for CLK input pins. Can we drive these pins through a standard LVDS, HR pins of ultrascale+ familiy FPGAs, configuring pins as LVDS ?

In ADC322x EVM they had used a 1:4 transformer before CLK input pins, do we need to use this structure before connecting to a standard LVDS?

regards,

serkan 

  • 0
    TI__Guru* 91947 points

    Serkan,

    If you AC couple the CLK signals you should be fine. I highly recommend though not to use any clock from an FPGA as they usually have very high phase noise which will degrade drastically your ADC performance. See section 9.3.2.1 of the data sheet for more information regarding this.

    Regards,

    Jim