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ADC32RF42EVM: Is there any problem with JESD204B interface

Long Hoang44
Intellectual 400 points
Part Number: ADC32RF42EVM
Other Parts Discussed in Thread: ADC32RF42

Hi,

I am using KC705 Xilinx Eval Board in order to process sampled analog data from ADC42RF42EVM through JESD204B interface. However, I just check them out and see the incompatibility as in the attached pictures.

Pin A14 A15 A18 A19 B12 B13 B16 B17 in FMC HPC connector of KC705 are all not connected while those pins should be DA0-DA3 in JESD channel B of ADC32RF42.

It means that I can only use JESD interface only for channel A if I do use KC705, right? What am I supposed to do if I want to use both JESD at channel A and B as being connected with KC705?

Thank you

  • 0
    TI__Guru* 91947 points

    Long,

    Since the KC705 only routed 4 receive lanes, you cannot get channel A to work when using the TI EVM with this board. You can use a VC707, as this board routes 8 receiver lanes, or build an adapter to re-route the serdes lanes between the ADC EVM and the KC705 and use two lanes for each channel.

    Regards,

    Jim

  • 0 in reply to jim s
    TI__Guru* 91947 points

    Long,

    The GTEX2 transceivers with speed grade -2 devices used on the Xilinx development platforms

    have a maximum rate of 10.3125 Gbps. In addition, the KC705 transceivers have a frequency band gap

    from 8 Gbps to 9.8 Gbp. After talking with Xilinx, they feel you should be OK to sample the ADC at 1.5G in 12 bit mode. This will have the serdes rate right at 8Gbps.

    You should be able to use one channel (B) with four lanes to do this.

    Regards,

    Jim