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ADS7864: What happens in FIFO mode if all 6 FIFO registers are filled?

Thomas Lorenz
Prodigy 10 points
Part Number: ADS7864


Hi

In my appliaction I have a continuous hold sequence (A,B, C, A ...) , address lines are tied to 1 (FIFO mode) but I delay reading data until a certain number of hold signals was given out.

The questoin is what happens to the FIFO buffer in such a case. Is it frozen und tile first read, which data is added next. Or is it shifing old data out and adds new one after every new conversion? Or something elese?

Regards

Thomas Lorenz

  • 0
    TI__Guru 55466 points
    Hi Thomas,

    Sorry for the delay in the response. Essentially the FIFO (First In First Out) is filled in the same order as you trigger conversions by toggling HOLDx pins. The FIFO is emptied as you read conversions, and you will read the conversion results in the same order the conversions were triggered. For every HOLDx signal triggered, two FIFO registers are filled.

    To answer your question, if all 6 FIFO registers are filled, and for example, a new conversion HOLDA is triggered, the FIFO will shift the register 0, register 1 data out (first in, first out), shift the data, and add the new Ch A0 and CH A1 conversion results on reg, 4 and reg. 5, keeping the same order as the conversions were triggered.

    Thank you,

    Best Regards,
    Luis