Sheet 5 of the TLV5614 datasheet specifies that AVDD and DVDD cannot be more than +/- 2.8V apart. Does this hold true when PD is held low?
Specific application, AVDD (5V) is sequenced earlier than DVDD (3V3) and there may be up to a 5.25V difference between the two rails indefinitely. PD is tied to DVDD (3V3).
The datasheet does not specify sequencing requirements, or considerations for when PD is low, can you clarify if the above implementation meets the device requirements?