• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 46 subscribers
  • Views 298 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DAC38RF80: DAC38RF80 JESD204B set-up?

HENRY JUNG
Expert 2030 points
Part Number: DAC38RF80

DEARS.

Customer is considering developing the DAC38RF80.
The JESD204B of the DAC38RF80 was calculated as follows.
Please review our settings.
If our settings are wrong, please suggest the correct settings.

DAC38RF80 set up

Complex Input
Clock In : 230.4Mhz
BW : 200Mhz
Interpolation : x24
K=32
LMFS : 4421
LANE RATE : 4608Mbps
Sysref : 7.2Mzh

Thank you.

  • 0
    TI__Genius 9695 points
    Hi Henry,

    No issues with this setting. The final sample rate will be 5529.6MHz ( 24 X 230.4MHz) which can be supported by the on-chip PLL. If possible I will recommend you increase the input clock frequency so that the BW is less than 0.8*Clock In? This will ensure better image rejection by the interpolation filters.

    Thanks,
    Eben.