This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADC12J4000: About ADC12J4000EVM

Part Number: ADC12J4000
Other Parts Discussed in Thread: LMK04828, TRF3765,


    The clock circuit of development board ADC12J4000 includes TRF3765 and LMK04828. It is found that the clock given to FPGA is contrary to the polarity of the clock(DEVCLKARX_P/N).What is the effect of this?

    Thank you!

  • Hi User,
    We have received your question, and I have forwarded it to an engineer familiar with the ADC12J400.
    Best Regards,
  • Hi user
    I'm not sure I understand your question regarding clock polarity to the FPGA. There are 3 differential clock type signals sent to the FPGA. These are DEVCLKARX_P/N, DEVCLKBRX_P/N and SYSREF_RX_P/N. All of these signals are the conventional polarity for the FMC connector and LMK04828 clock source.
    There is an intentional polarity inversion for all of the ADC high speed serial data pairs sent to the FMC connector. Signals Dn_P/N are all inverted to the conventional FMC pin mapping polarities. This inversion was done to avoid vias or other routing problems required if the standard polarity was used. We compensate for this polarity inversion in the JESD204B capture firmware.
    If this doesn't answer your question please provide more details regarding the specific signal names you are referring to.
    Best regards,
    Jim B