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AMC1203: AMC1203 Issue

Part Number: AMC1203
Other Parts Discussed in Thread: ADS1202


I have several questions about the AMC1203. Can you help me to explain them ASAP?

1. Whether the OSR in the AMC1203 document is the same concept as the decimation ratio in the sinc3 filter?With 256?

2. Is the decimation ratio the divider factor of MCLK clock?

3. Combining the ADS1202 with an FPGA Digital Filter for Current Measurement in Motor Control Applications

In this document, the Sinc3's filter(designed by FPGA) bus output bandwidth is 25 bits. The question is how is the result of the final output corresponding to a 16-bit sampling resolution (AMC1203 written document is a 16-bit resolution)?

About the third question, in the document Combining the ADS1202 with an FPGA Digital Filter for Current Measurement in Motor Control Applications,  the final output data CN5 is 25(which can be found in VHDL program), but in the recent VHDL (slac055) download file, CN5 is 24.

In slac055 : When the decimation ratio is 256, pick the higher 16 bits as the output value, so I want to ask what we should choose for CN5.25 bits or 24 bits?

Best regards

  • Hi Lenna,

    If you take a look throughout the various specification tables in the AMC1203 datasheet, you may notice that all items assume the use of a SINC3 filter with an OSR of 256. In this case, OSR and decimation ratio are the same concept. Decimation is not however a division of the MCLK - it's the accumulation and averaging of the samples to a lower data rate, the modulator clock speed remains constant. For the digital filter question, the concept of 'picking 16-bits' is strictly a matter of convenience. For example, if the sinc filter runs with a Sinc3 structure and an oversampling ratio of 256, the data values will be in the range of –16,777,216 to 16,777,216, which represents 25-bits. To get a maximum 16-bit range of –32,767 to 32,767, you would shift the data by 9 and retain the upper 16-bits of data.