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DDC114 Test Mode Noise

Other Parts Discussed in Thread: DDC114, REF3140, OPA350, OPA364

I have the DDC114 Development board and I have some custom software I wrote that can plug in and talk to the DDC114 and get readings. Using the development board I get very good results in both test mode and not in test mode. In test mode using the 3 pF cap I am seeing around 30 counts of noise, which is about what I expect.

I also have a board that was designed and layed out by my company that I can plug in exactly the same way and use the same software to talk to the DDC. But on this board I am getting around 100 counts of noise. The board was designed very similar to the dev board and careful consideration of routing and sheilding was observed in the layout.

What are some tips or things to make sure we are doing correctly to get our noise levels down there? Thank you.

  • Brad,

    Is  the board that your company built and you are using connected to the DDC114EVM, or does it contain the DDC114?  A couple of things to consider is external noise pickup and board cleanliness.  For example, we have found the noise increases significantly if there is the slightest flux residue between the input pins of the DDC114.

    Best regards,

    Bob B

  • If you are getting high noise in TEST mode, then the thing to check is the reference - this is the most common across-the-chip noise-causing node.  If you get good noise in TEST mode but bad noise when inputs are hooked up, then look into the inputs - if you use photodiodes, what Sensor capacitance are they?  Larger capactiance means higher noise.  If you use resistors, are they >=10Mohm?  Lower valued resistors cause higher noise.

    I hope this helps,

    Jason

  • Bob Benjamin said:

    Brad,

    Is  the board that your company built and you are using connected to the DDC114EVM, or does it contain the DDC114?  A couple of things to consider is external noise pickup and board cleanliness.  For example, we have found the noise increases significantly if there is the slightest flux residue between the input pins of the DDC114.

    Best regards,

    Bob B

     

    Thanks for the input. Our in-house board contains a DDC114 on it. We are not attaching to the DDC114EVM. I will look into the cleanliness and check for flux residue.

     

    Brad

  • Jason Bridgmon said:

    If you are getting high noise in TEST mode, then the thing to check is the reference - this is the most common across-the-chip noise-causing node.  If you get good noise in TEST mode but bad noise when inputs are hooked up, then look into the inputs - if you use photodiodes, what Sensor capacitance are they?  Larger capactiance means higher noise.  If you use resistors, are they >=10Mohm?  Lower valued resistors cause higher noise.

    I hope this helps,

    Jason

     

    Jason,

    Thanks you. I will look into the reference. We are using something different that a ref3140, it is a AD1584, the rest of the reference circuit matches the datasheet. Besides the reference is there anything else that I could look into?

     

    Brad

     

  • Brad,

    In test mode, there isn't much that affects the noise - the reference is the main contributer.  To a much lesser extent: the power supplies maybe, CLK jitter maybe, the point in time during the period that the data is read back (between /DVALIDs) maybe.

    If you use a switching power supply, you may see a degradation in performance, and if you don't have adequate bypass capacitance on the reference you may see it as well.

    I would really look at the reference - can you take the REF3140 from our EVM and put it on your board?  I believe the AD1584 and REF3140 are pin compatible SOT-23 devices.  I have not evaluated the AD1584 for noise performance on the DDC114 but I can say that I tried several 4.096V references not every reference at TI worked well as a reference for this device, which is why we recommend the REF3140.

    Also if you would be willing to share your schematic and layout with me directly (not through the forum), I would be happy to review it and let you know if I saw anything I thought might be an issue.  Since you followed the EVM design, you should be in pretty good shape though.

    Jason

  • Brad,

    I had another thought - if you do take the REF3140 off our EVM, you could put the AD1584 down in its place and see if our EVM shows the same degradation in noise performance.  That would be a pretty quick-and-easy test to evaluate the AD1584 as a reference device for the DDC, and would help us debug your solution faster!

    Jason

  • Jason,

    Thank you for the suggestions. I will try swapping out the reference and see if that makes a difference.

    Another difference between our board and the dev board is that we are using hard drive buffers, a 74lvc244 for the input pins on the DDC114 (ie, CLK, CONV, DCLK ...) And on the dev board it is using a drive with pullups. Could this be a culprit?

    How can I contact you to let you take a look at our layout?

    Thank you.

    Brad

  • Jason,

    Another item that is different in our schematic is we are using a different buffer in our reference circuit. We are using a OPA364DBV instead of the OPA350

     

    Brad

  • Brad,

    My email is bridgmon_jason'at'ti.com

    The digital line drivers probably aren't a problem, but the reference buffer being an OPA364 might be the culprit.  I haven't personally tried the OPA364 so I don't know how it performs, but I know the OPA350 can drive large capacitive loads in unity gain, which not all op amps can do.

    The OPA364DBV does not look pin compatible with any package of OPA350, so swapping that part out to test configurations may not be so easy.

    Jason