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DAC084S085: About SPI specification

Tao_2199
Genius 5700 points
Part Number: DAC084S085

Hello,

 

About SPI specification

 

Regarding to SPI specificationon DAC084S085, my customer is asking a question.　

(Question)

(1)

According to Figure 1.(datasheet page 6), SCLK is input before SYNC pulse.

Is SCLK needed before SYNC pulse?

I understand that SPI SCLK is input after CS(SYNC) falling edge generally.


 

(2)

About SPI mode (CPOL/CPHA),

What mode is supported on DAC084S085?

I think that SPI mode will be mode1(CPHA=1/CPOL=0) from Figure 1.

My understanding is correct?

 

Regards,

Tao 2199


  • 0
    TI__Genius 14220 points
    Hi Tao,

    Thank you for your query.

    1) You don't need SCLK before SYNC falling edge.
    2)The SPI Mode is CPOL = 0 and CPHA =1, as you have mentioned.

    Hope that answers.

    Regards,
    Uttam Sahu
    Applications Engineer, Precision DACs
  • 0 in reply to Uttam Sahu
    Genius 5700 points

    Hello Uttam,

     

    Thank you for reply.

    I informed to your answer and they understood about SPI specification.

    And they have an additional question.

     

    (Question)

    According to 7.6 Timing Requirements.(datasheet page 7), tss is characterized as following.



     

    So, tss should be set more than 10ns at SPI mode1,

    (Any way, when SPI SCLK is 40MHz(max), tss have a margin.)


     

    My understanding is correct? Just in case, I’m asking about it.

     

     

    Regards,

    Tao 2199

  • 0 in reply to Tao_2199
    TI__Genius 14220 points
    Hi Tao,

    Your interpretation is correct.

    Regards,
    Uttam