ADS54J40: ADS54J40 JESD204B Link Setup Failure

TAYLAN ERTAŞ

Part Number: ADS54J40
Other Parts Discussed in Thread: LMK04828,

Hello Everyone,

Our hardware consists of Zynq-7045, LMK04828 clock generator and ADS54J40 ADC. We have some problems about JESD link setup. We are planning to use one of LMFS=8224 and LMFS=4211 configurations.

We can setup JESD link successfully only when LMFS=8224 and K=16 (not any other K values or configurations). K can be any other value actually, right?
We observe that SYNC signal toggles and JESD RX IP core can receive K28.5 CGS data in both configurations. However, ILA configuration registers (ILA CFG:0-7) are invalid except for LMFS=8224 and K=16 when monitoring JESD RX IP registers. (see the files ila_cfg_reg_lmfs_8224_k16.txt and ila_cfg_reg_lmfs_4221_k32.txt)
In the case of LMFS=8224 and K=16, we observe that ILA CFG-3 registers of two lanes of channel-A are the same (LID(b20:b16) field should be different). Therefore, We cannot get data from one lane of Channel-A. The same obervation is valid for Channel-B also. How is this possible? we checked all configurations and FPGA pin assignment constraints many times and we couldn't find anything. (see the files ila_cfg_reg_lmfs_8224_k16.txt and ila_cfg_reg_lmfs_4211_k32.txt)

Platform: Vivado 2015.2 (JESD IP: V6.1)

Configuration LMFS=8224:

a. LMFS: 8224, HD=0, No Decimation, No scrambling, K=16

b. ADCCLK = 800 MHz (F_adc = 800 Msps) => F_line = 4 Gbps.

c. F_LMFC = F_line/10/F/K=12.5 MHz, F_SYSREF=F_LMFC/(2^n-integer)=3.125 MHz for n-integer = 2, and F_SYSREF <= 250/ (F*K)=7.8125 MHz

Configuration LMFS=4221:

a. LMFS: 4221, HD=1, No Decimation, No scrambling, K=32

b. ADCCLK = 800 MHz (F_adc = 800 Msps) => F_line = 8 Gbps.

c. F_LMFC = F_line/10/F/K=25 MHz, F_SYSREF=F_LMFC/(2^n-integer)=3.125 MHz for n-integer = 3, and F_SYSREF <= 250/ (F*K)=7.8125 MHz

We have attached our ADC configuration settings to load it from ADS54J40 EVM GUI. Since we have no ADS54J40 EVM board, we cannot verify it yet.

In addition to this, we configure more ADC registers in our software, so you may check them in the file "hal_adc.c".

ila_cfg_reg_lmfs_8224_k16.txt

// 		CFG-0 	CFG-1 	CFG-2 	CFG-3 		CFG-4 	CFG-5 	CFG-6 	CFG-7
JESD IP Lane-0: 1 	1 	15 	117571584 	986369	768 	3801088  0
JESD IP Lane-1: 1 	1 	15 	117440512 	986369  768 	3670016  0
JESD IP Lane-2: 1 	1 	15 	117440512 	986369  768 	3670016  0
JESD IP Lane-3: 1 	1 	15 	117506048 	986369  768	3735552  0
JESD IP Lane-4: 1 	1 	15 	117833728 	986369  768 	4063232  0
JESD IP Lane-5: 1 	1 	15 	117702656 	986369  768 	3932160  0
JESD IP Lane-6: 1 	1 	15 	117702656 	986369  768 	3932160  0
JESD IP Lane-7: 1 	1 	15 	117768192 	986369  768 	3997696  0

ila_cfg_reg_lmfs_4211_k32.txt

// 		CFG-0 	CFG-1 	CFG-2 	CFG-3 		CFG-4 	CFG-5 		CFG-6 		CFG-7
JESD IP Lane-0: 0, 	2, 	3, 	50465820, 	66307, 	16780544, 	32781, 		9, 
JESD IP Lane-1: 1, 	0, 	31, 	50462720, 	986369, 65536, 		4390912, 	0,

ADS54J40_LMF_8224_te.cfg

adc_lmfs_4211_te.cfg

hal_adc.c

// ===========================================================================
// Include Files
// ---------------------------------------------------------------------------
#include "hal_dbg.h"
#include "hal_adc.h"
#include "hal_lmk.h"
#include "hal_pl.h"
#include "hal_spi.h"
#include "hal_timer.h"

// ===========================================================================
// External Data Definitions
// ---------------------------------------------------------------------------

// ===========================================================================
// Local Defines
// ---------------------------------------------------------------------------
#define ADC_DEFAULT_REGS_LENGTH					38//54

// ===========================================================================
// Local Structures
// ---------------------------------------------------------------------------

// ===========================================================================
// Local Data Definitions
// ---------------------------------------------------------------------------
SPI_HANDLE_Type	*adc_spi_handle;

#if HW_CFG_ENABLE_ADC_LMFS_8224
// LMFS=8224, HD=0, No Decimation, Power Down Chl-A
const u16 adc_default_cfg_regs[ADC_DEFAULT_REGS_LENGTH][2] = {
	{0x0000, 	0x81},		// Internal Soft Reset
	{0x4001, 	0x00},		// Clear any unwanted content from the unused pages of the JESD bank.
	{0x4002, 	0x00},		// Clear any unwanted content from the unused pages of the JESD bank.

	{0x0011, 	0x80},		// Select Analog SPI-Master page
	{0x0020, 	0x00},		// PowerDown Mask-1: PDN_ADC_CHA[b7:b6]=0-Normal, PDN_ADC_CHB[b5:b4]=0-Normal
	{0x0021, 	0x00},		// PowerDown Mask-1: PDN_BUFFER_CHB[b7:b6]=0-Normal, PDN_BUFFER_CHA[b5:b4]=0-Normal
	{0x0023, 	0x10},		// PowerDown Mask-2: PDN_ADC_CHA[b7:b6]=1-PwrDwn, PDN_ADC_CHB[b5:b4]=0-Normal
	{0x0024, 	0x10},		// PowerDown Mask-2: PDN_BUFFER_CHB[b7:b6]=0-Normal, PDN_BUFFER_CHA[b5:b4]=1-PwrDwn
{0x0026, 	0x00},//0x20},		// GLOBAL_PDN[b7]=0-Normal, OVERRIDE_PDN_PIN[b6]=0-Normal, PDN_MASK_SEL[b5]=1-PwrDwnMask2 (0-PwrDwnMask1)
	{0x004F, 	0x00},		// EN_INPUT_DC_COUPLING[b0]=0-Disable
	{0x0053, 	0x00},		// MASK_SYSREF[b6]=0-Normal, EN_SYSREF_DC_COUPLING[b1]=0-Normal/Disable
	{0x0055, 	0x00},		// PDN_MASK[b4]=0-Normal

	{0x4004, 	0x68},		// Select Digital SPI-Main Digital page
	{0x4003, 	0x00},		// Select Digital SPI-Main Digital page
	{0x60F7, 	0x01},		// DIG_RESET[b0]=1-Reset for CHL-A (self-clearing bit)
//	{0x70F7, 	0x01},		// DIG_RESET[b0]=1-Reset for CHL-B (self-clearing bit)
	{0x6000, 	0x01},		// PULSE_RESET[b0]=1-Reset for CHL-A
	{0x6000, 	0x00},		// PULSE_RESET[b0]=0-Normal
//	{0x7000, 	0x01},		// PULSE_RESET[b0]=1-Reset for CHL-B
//	{0x7000, 	0x00},		// PULSE_RESET[b0]=0-Normal

	{0x0011, 	0x80},		// Select Analog SPI-Master page
	{0x0059, 	0x20},		// FOVR_CHB[b7]=0-Normal, b[5]=1-Always

	{0x4004, 	0x69},		// Select Digital SPI-JESD Digital page
	{0x4003, 	0x00},		// Select Digital SPI-JESD Digital page
	{0x6000, 	0x80},		// CTRL_K[b7]=1-MultiframeinReg6, TEST_MODE_EN[b4]=0-Disable, FLIP_ADC_DATA[b3]=0-Normal, LANE_ALIGN[b2]=0-Normal (1-Insert K28.3), FRAME_ALIGN[b1]=0-Normal(1-Insert K28.7), TX_LINK_DIS[b0]=0-Normal(1-ILA Disabled),
	{0x6001, 	0x01},		// TODO: SYNC_REG[b7]=0-Normal, SYNC_REG_EN[b6]=0-Use SYNC_N pin (1-Use SYNC_REG), JESD_FILTER[b5:b3]=0-Bypass, JESD_MODE[b2:b0]=1-20X,four lanes per ADC
	{0x6002, 	0x00},		// LINK_LAYER_TESTMODE[b7:b5]=0-Normal(1-D21.5 / 2-K28.5 / 3-ILA seq), LINK_LAYER_RPAT[b4]=0-Normal, LMFC_MASK_RESET[b3]=0-LMFC Reset not masked
	{0x6003, 	0x00},		// FORCE_LMFC_COUNT[b7]=0-Normal, MASK_SYSREF[b6:b2]=0-, RELEASE_ILANE_SEQ[b1:b0]=0-0 Multiframe delay
	{0x6005, 	0x00},		// SCRAMBLE_EN[7]=0-Disable
	{0x6006, 	0x0F},		// K[b4:b0]=0x0F-16 (F_sysref <= 250/(F*K)=7.8125 MHz)
	{0x6007, 	0x08},		// SUBCLASS[b3]=1- Subclass1
	{0x6016, 	0x80},		// [b7]=1 (Always), LANE_SHARE[b5]=0-Normal/Disable,
	{0x6031, 	0x0B},		// DA_BUS_REORDER[b7:b0]=0xB (0xA only for LMFS=1241, 4X, JESD_MODE=2)
	{0x6032, 	0x0B},		// DB_BUS_REORDER[b7:b0]=0xB (0xA only for LMFS=1241, 4X, JESD_MODE=2)
/*	{0x7000, 	0x80},		// CTRL_K[b7]=1-MultiframeinReg6, TEST_MODE_EN[b4]=0-Disable, FLIP_ADC_DATA[b3]=0-Normal, LANE_ALIGN[b2]=0-Normal (1-Insert K28.3), FRAME_ALIGN[b1]=0-Normal(1-Insert K28.7), TX_LINK_DIS[b0]=0-Normal(1-ILA Disabled),
	{0x7001, 	0x04},		// TODO: SYNC_REG[b7]=0-Normal, SYNC_REG_EN[b6]=0-Use SYNC_N pin (1-Use SYNC_REG), JESD_FILTER[b5:b3]=0-Bypass, JESD_MODE[b2:b0]=4-40X,LMSF=4211 only
	{0x7002, 	0x00},		// LINK_LAYER_TESTMODE[b7:b5]=0-Normal(1-D21.5 / 2-K28.5 / 3-ILA seq), LINK_LAYER_RPAT[b4]=0-Normal, LMFC_MASK_RESET[b3]=0-LMFC Reset not masked
	{0x7003, 	0x00},		// FORCE_LMFC_COUNT[b7]=0-Normal, MASK_SYSREF[b6:b2]=0-, RELEASE_ILANE_SEQ[b1:b0]=0-0 Multiframe delay
	{0x7005, 	0x00},		// SCRAMBLE_EN[7]=0-Disable
	{0x7007, 	0x08},		// SUBCLASS[b3]=1- Subclass1
	{0x7016, 	0x80},		// [b7]=1 (Always), LANE_SHARE[b5]=0-Normal/Disable,
	{0x7031, 	0x0B},		// DA_BUS_REORDER[b7:b0]=0xB (0xA only for LMFS=1241, 4X, JESD_MODE=2)
	{0x7032, 	0x0B},		// DB_BUS_REORDER[b7:b0]=0xB (0xA only for LMFS=1241, 4X, JESD_MODE=2)
	{0x7006, 	0x0F},		// K[b4:b0]=0x0F-16 (F_sysref <= 250/(F*K)=7.8125 MHz)
*/
	{0x4004, 	0x6A},		// Select Digital SPI-JESD Analog page
	{0x4003, 	0x00},		// Select Digital SPI-JESD Analog page
	{0x6012, 	0x00},		// TODO: SEL_EMP_LANE_1[b7:b2]=0-0 dB, [b1:b0]=0-Always
//	{0x7012, 	0x00},		// TODO: SEL_EMP_LANE_1[b7:b2]=0-0 dB, [b1:b0]=0-Always
	{0x6016, 	0x00},		// JESD_PLL_MODE[b1:b0]=0-(20X, 4 lanes per ADC)
//	{0x7016, 	0x00},		// JESD_PLL_MODE[b1:b0]=0-(20X, 4 lanes per ADC)
	{0x601B, 	0x00},		// JESD_SWING[b7:b5]=0-860 mVpp, FOVR_CHA_EN[b3]=0-Normal (1-PDN is overwritten)
//	{0x701B, 	0x00},		// JESD_SWING[b7:b5]=0-860 mVpp, FOVR_CHA_EN[b3]=0-Normal (1-PDN is overwritten)
	{0x4004, 	0x00},		//
	{0x4003, 	0x00}		//
};

#elif 1
// LMFS=4211, HD=1, No Decimation, Power Down Chl-A
const u16 adc_default_cfg_regs[ADC_DEFAULT_REGS_LENGTH][2] = {
	{0x0000, 	0x81},		// Internal Soft Reset
	{0x4001, 	0x00},		// Clear any unwanted content from the unused pages of the JESD bank.
	{0x4002, 	0x00},		// Clear any unwanted content from the unused pages of the JESD bank.

	{0x0011, 	0x80},		// Select Analog SPI-Master page
	{0x0020, 	0x00},		// PowerDown Mask-1: PDN_ADC_CHA[b7:b6]=0-Normal, PDN_ADC_CHB[b5:b4]=0-Normal
	{0x0021, 	0x00},		// PowerDown Mask-1: PDN_BUFFER_CHB[b7:b6]=0-Normal, PDN_BUFFER_CHA[b5:b4]=0-Normal
	{0x0023, 	0x10},		// PowerDown Mask-2: PDN_ADC_CHA[b7:b6]=1-PwrDwn, PDN_ADC_CHB[b5:b4]=0-Normal
	{0x0024, 	0x10},		// PowerDown Mask-2: PDN_BUFFER_CHB[b7:b6]=0-Normal, PDN_BUFFER_CHA[b5:b4]=1-PwrDwn
{0x0026, 	0x00},//0x20},		// GLOBAL_PDN[b7]=0-Normal, OVERRIDE_PDN_PIN[b6]=0-Normal, PDN_MASK_SEL[b5]=1-PwrDwnMask2 (0-PwrDwnMask1)
	{0x004F, 	0x00},		// EN_INPUT_DC_COUPLING[b0]=0-Disable
	{0x0053, 	0x00},		// MASK_SYSREF[b6]=0-Normal, EN_SYSREF_DC_COUPLING[b1]=0-Normal/Disable
	{0x0055, 	0x00},		// PDN_MASK[b4]=0-Normal

	{0x4004, 	0x68},		// Select Digital SPI-Main Digital page
	{0x4003, 	0x00},		// Select Digital SPI-Main Digital page
	{0x60F7, 	0x01},		// DIG_RESET[b0]=1-Reset for CHL-A (self-clearing bit)
//	{0x70F7, 	0x01},		// DIG_RESET[b0]=1-Reset for CHL-B (self-clearing bit)
	{0x6000, 	0x01},		// PULSE_RESET[b0]=1-Reset for CHL-A
	{0x6000, 	0x00},		// PULSE_RESET[b0]=0-Normal
//	{0x7000, 	0x01},		// PULSE_RESET[b0]=1-Reset for CHL-B
//	{0x7000, 	0x00},		// PULSE_RESET[b0]=0-Normal

	{0x0011, 	0x80},		// Select Analog SPI-Master page
	{0x0059, 	0x20},		// FOVR_CHB[b7]=0-Normal, b[5]=1-Always

	{0x4004, 	0x69},		// Select Digital SPI-JESD Digital page
	{0x4003, 	0x00},		// Select Digital SPI-JESD Digital page
	{0x6000, 	0x80},		// CTRL_K[b7]=1-MultiframeinReg6, TEST_MODE_EN[b4]=0-Disable, FLIP_ADC_DATA[b3]=0-Normal, LANE_ALIGN[b2]=0-Normal (1-Insert K28.3), FRAME_ALIGN[b1]=0-Normal(1-Insert K28.7), TX_LINK_DIS[b0]=0-Normal(1-ILA Disabled),
	{0x6001, 	0x04},		// TODO: SYNC_REG[b7]=0-Normal, SYNC_REG_EN[b6]=0-Use SYNC_N pin (1-Use SYNC_REG), JESD_FILTER[b5:b3]=0-Bypass, JESD_MODE[b2:b0]=4-40X,LMSF=4211 only
	{0x6002, 	0x00},		// LINK_LAYER_TESTMODE[b7:b5]=0-Normal(1-D21.5 / 2-K28.5 / 3-ILA seq), LINK_LAYER_RPAT[b4]=0-Normal, LMFC_MASK_RESET[b3]=0-LMFC Reset not masked
	{0x6003, 	0x00},		// FORCE_LMFC_COUNT[b7]=0-Normal, MASK_SYSREF[b6:b2]=0-, RELEASE_ILANE_SEQ[b1:b0]=0-0 Multiframe delay
	{0x6005, 	0x00},		// SCRAMBLE_EN[7]=0-Disable
	{0x6006, 	0x1F},		// K[b4:b0]=0x1F-32 (F_sysref <= 250/(F*K)=7.8125 MHz)
	{0x6007, 	0x08},		// SUBCLASS[b3]=1- Subclass1
	{0x6016, 	0x80},		// [b7]=1 (Always), LANE_SHARE[b5]=0-Normal/Disable,
	{0x6031, 	0x0B},		// DA_BUS_REORDER[b7:b0]=0xB (0xA only for LMFS=1241, 4X, JESD_MODE=2)
	{0x6032, 	0x0B},		// DB_BUS_REORDER[b7:b0]=0xB (0xA only for LMFS=1241, 4X, JESD_MODE=2)
/*	{0x7000, 	0x80},		// CTRL_K[b7]=1-MultiframeinReg6, TEST_MODE_EN[b4]=0-Disable, FLIP_ADC_DATA[b3]=0-Normal, LANE_ALIGN[b2]=0-Normal (1-Insert K28.3), FRAME_ALIGN[b1]=0-Normal(1-Insert K28.7), TX_LINK_DIS[b0]=0-Normal(1-ILA Disabled),
	{0x7001, 	0x04},		// TODO: SYNC_REG[b7]=0-Normal, SYNC_REG_EN[b6]=0-Use SYNC_N pin (1-Use SYNC_REG), JESD_FILTER[b5:b3]=0-Bypass, JESD_MODE[b2:b0]=4-40X,LMSF=4211 only
	{0x7002, 	0x00},		// LINK_LAYER_TESTMODE[b7:b5]=0-Normal(1-D21.5 / 2-K28.5 / 3-ILA seq), LINK_LAYER_RPAT[b4]=0-Normal, LMFC_MASK_RESET[b3]=0-LMFC Reset not masked
	{0x7003, 	0x00},		// FORCE_LMFC_COUNT[b7]=0-Normal, MASK_SYSREF[b6:b2]=0-, RELEASE_ILANE_SEQ[b1:b0]=0-0 Multiframe delay
	{0x7005, 	0x00},		// SCRAMBLE_EN[7]=0-Disable
	{0x7006, 	0x1F},		// K[b4:b0]=0x1F-32 (F_sysref <= 250/(F*K)=7.8125 MHz)
	{0x7007, 	0x08},		// SUBCLASS[b3]=1- Subclass1
	{0x7016, 	0x80},		// [b7]=1 (Always), LANE_SHARE[b5]=0-Normal/Disable,
	{0x7031, 	0x0B},		// DA_BUS_REORDER[b7:b0]=0xB (0xA only for LMFS=1241, 4X, JESD_MODE=2)
	{0x7032, 	0x0B},		// DB_BUS_REORDER[b7:b0]=0xB (0xA only for LMFS=1241, 4X, JESD_MODE=2)
*/

	{0x4004, 	0x6A},		// Select Digital SPI-JESD Analog page
	{0x4003, 	0x00},		// Select Digital SPI-JESD Analog page
	{0x6012, 	0x00},		// TODO: SEL_EMP_LANE_1[b7:b2]=0-0 dB, [b1:b0]=0-Always
	//{0x7012, 	0x00},		// TODO: SEL_EMP_LANE_1[b7:b2]=0-0 dB, [b1:b0]=0-Always
	{0x6016, 	0x02},		// JESD_PLL_MODE[b1:b0]=2-(40X, 2 lanes per ADC)
	//{0x7016, 	0x02},		// JESD_PLL_MODE[b1:b0]=2-(40X, 2 lanes per ADC)
	{0x601B, 	0x00},		// JESD_SWING[b7:b5]=0-860 mVpp, FOVR_CHA_EN[b3]=0-Normal (1-PDN is overwritten)
	//{0x701B, 	0x00},		// JESD_SWING[b7:b5]=0-860 mVpp, FOVR_CHA_EN[b3]=0-Normal (1-PDN is overwritten)
	{0x4004, 	0x00},		//
	{0x4003, 	0x00}		//
};

#else
const u16 adc_default_cfg_regs[ADC_DEFAULT_REGS_LENGTH][2]= {
	{0x0011, 	0x80},		// Select Analog SPI-Master page
	{0x0011, 	0x0F},		// Select Analog SPI-ADC page


	{0x4004, 	0x68},		// Select Digital SPI-Main Digital page
	{0x4003, 	0x00},		// Select Digital SPI-Main Digital page

	{0x4004, 	0x69},		// Select Digital SPI-JESD Digital page
	{0x4003, 	0x00},		// Select Digital SPI-JESD Digital page

	{0x4004, 	0x6A},		// Select Digital SPI-JESD Analog page
	{0x4003, 	0x00},		// Select Digital SPI-JESD Analog page


	{0x0005, 	0x00},		// DISABLE_BROADCAST[b0]=0-Program Chl-A/B as pair

	{0x0011, 	0x80},		// Select Analog SPI-Master page
	{0x0020, 	0x00},		// PowerDown Mask-1: PDN_ADC_CHA[b7:b6]=0-Normal, PDN_ADC_CHB[b5:b4]=0-Normal
	{0x0021, 	0x00},		// PowerDown Mask-1: PDN_BUFFER_CHB[b7:b6]=0-Normal, PDN_BUFFER_CHA[b5:b4]=0-Normal
	{0x0023, 	0x00},		// PowerDown Mask-2: PDN_ADC_CHA[b7:b6]=0-Normal, PDN_ADC_CHB[b5:b4]=0-Normal
	{0x0024, 	0x00},		// PowerDown Mask-2: PDN_BUFFER_CHB[b7:b6]=0-Normal, PDN_BUFFER_CHA[b5:b4]=0-Normal
	{0x0026, 	0xC0},		// GLOBAL_PDN[b7]=0-Normal, OVERRIDE_PDN_PIN[b6]=0-Normal, PDN_MASK_SEL[b5]=0-PwrDwnMask1
	{0x004F, 	0x00},		// EN_INPUT_DC_COUPLING[b0]=0-Disable
	{0x0053, 	0x00},		// MASK_SYSREF[b6]=0-Normal, EN_SYSREF_DC_COUPLING[b1]=0-Normal/Disable
	{0x0055, 	0x00},		// PDN_MASK[b4]=0-Normal
	{0x0059, 	0x20},		// FOVR_CHB[b7]=0-Normal, b[5]=1-Always

	{0x0011, 	0x0F},		// Select Analog SPI-ADC page
	{0x005F, 	0x0F},		// FOVR_THRESHOLD[b7:b0]=0xE3

	{0x4004, 	0x68},		// Select Digital SPI-Main Digital page
	{0x4003, 	0x00},		// Select Digital SPI-Main Digital page
	{0x6000, 	0x00},		// PULSE_RESET[b0]=0-Normal
	{0x6041, 	0x00},		// DECFIL_MODE_3[b5]=0, DECFIL_EN[b4]=0-Disable, DECFIL_MODE_2_0[b2:b0]=0 (DecFilMode=0-Bpass centered on fsx3/16, 4X)
	{0x6042, 	0x00},		// NYQUIST_ZONE[b2:b0]=0-1st Zone (0-500 MHz)
	{0x6043, 	0x00},		// FORMAT_SEL[b0]=0-2s complement
	{0x6044, 	0x7F},		// DIGITAL_GAIN[b6:b0]=0x7F-Gain 9.5 dB (20log(gain/32))
	{0x604B, 	0x00},		// FORMAT_EN[b5]=0-Output in 2s complement
	{0x604D, 	0x00},		// DEC_MOD_EN[b3]=0-Disable
	{0x604E, 	0x00},		// CTRL_NYQUIST[b7]=0-Disable
	{0x6052, 	0x00},		// DIG_GAIN_EN[b0]=0-Disable
	{0x60AB, 	0x00},		// LSB_SEL_EN[b0]=0-Disable (1-LSB can be programmed as fast OVR)
	{0x60AD, 	0x00},		// LSB_SELECT[b1:b0]=0-LS bits are zeros ( 1-LS bits are FOVR info)
	{0x60F7, 	0x00},		// DIG_RESET[b0]=0-Normal (self-clearing bit)

	{0x4004, 	0x69},		// Select Digital SPI-JESD Digital page
	{0x4003, 	0x00},		// Select Digital SPI-JESD Digital page
	{0x6000, 	0x80},		// CTRL_K[b7]=1-MultiframeinReg6, TEST_MODE_EN[b4]=0-Disable, FLIP_ADC_DATA[b3]=0-Normal, LANE_ALIGN[b2]=0-Normal (1-Insert K28.3), FRAME_ALIGN[b1]=0-Normal(1-Insert K28.7), TX_LINK_DIS[b0]=0-Normal(1-ILA Disabled),
	{0x6001, 	0x02},		// SYNC_REG[b7]=0-Normal, SYNC_REG_EN[b6]=0-Use SYNC_N pin (1-Use SYNC_REG), JESD_FILTER[b5:b3]=0-Bypass, JESD_MODE[b2:b0]=4-40x (LMSF=4211 only)
	{0x6002, 	0x00},		// LINK_LAYER_TESTMODE[b7:b5]=0-Normal(1-D21.5 / 2-K28.5 / 3-ILA seq), LINK_LAYER_RPAT[b4]=0-Normal, LMFC_MASK_RESET[b3]=0-LMFC Reset not masked
	{0x6003, 	0x00},		// FORCE_LMFC_COUNT[b7]=0-Normal, MASK_SYSREF[b6:b2]=0-, RELEASE_ILANE_SEQ[b1:b0]=0-0 Multiframe delay,
	{0x6005, 	0x00},		// SCRAMBLE_EN[7]=0-Disable
	{0x6006, 	0x0F},		// K[b4:b0]=0xF-16
	{0x6007, 	0x08},		// SUBCLASS[b3]=1- Subclass1
	{0x6016, 	0x80},		// [b7]=1 (Always), LANE_SHARE[b5]=0-Normal/Disable,
	{0x6031, 	0x0B},		// DA_BUS_REORDER[b7:b0]=0xB (0xA only for LMFS=1241, 4X, JESD_MODE=2)
	{0x6032, 	0x0B},		// DB_BUS_REORDER[b7:b0]=0xB (0xA only for LMFS=1241, 4X, JESD_MODE=2)

	{0x4004, 	0x6A},		// Select Digital SPI-JESD Analog page
	{0x4003, 	0x00},		// Select Digital SPI-JESD Analog page
	{0x6012, 	0x00},		// SEL_EMP_LANE_1[b7:b2]=0-0 dB
	{0x6013, 	0x00},		// SEL_EMP_LANE_0[b7:b2]=0-0 dB
	{0x6014, 	0x00},		// SEL_EMP_LANE_2[b7:b2]=0-0 dB
	{0x6015, 	0x00},		// SEL_EMP_LANE_3[b7:b2]=0-0 dB
	{0x6016, 	0x02},		// JESD_PLL_MODE[b1:b0]=2-(40X, 2 lanes per ADC)
	{0x601A, 	0x00},		// FOVR_CHA[b1]=0-Normal (1-it outputs FOVR signal on PDN pin)
	{0x601B, 	0x00},		// JESD_SWING[b7:b5]=0-860 mVpp, FOVR_CHA_EN[b3]=0-Normal (1-PDN is overwritten)
};
#endif

u16 adc_regs[ADC_DEFAULT_REGS_LENGTH];

u32 reg_jesd_rx[3];
u32 reg_jesd_rx_lane[8][13];

u8  adc_tps_0 = 255;
u8  adc_tps_1 = 8;
u8  adc_tps_2 = 9;
u8  adc_tps_3 = 10;

// ===========================================================================
// Local Prototype Declarations
// ---------------------------------------------------------------------------

// ===========================================================================
// External Data Declarations
// ---------------------------------------------------------------------------

// ===========================================================================
// Module Body
// ---------------------------------------------------------------------------

//----------------------------------------------------------------------------
// Function Name		: hal_adc_init()
//
// Function Description	:
//
// Input Argument(s)	: No input
//
// Return Argument		: void
//----------------------------------------------------------------------------
void hal_adc_init(void) {

	u16 k;

	// Init parameters
	adc_spi_handle = &spi_1_handle;

	// Init gpio
	hal_adc_init_gpio();

	// Power Up (T_pwr = 1 ms)
	hal_adc_set_gpio_pwr_dwn(ENABLE);
	hal_timer_delay_msec(10);
	hal_adc_set_gpio_pwr_dwn(DISABLE);
	hal_timer_delay_msec(10);

	// Reset ADC device (T_pulse = 10 ns)
	hal_adc_set_gpio_reset(ENABLE);
	hal_timer_delay_usec(10);
	hal_adc_set_gpio_reset(DISABLE);

	// Wait for T_reset = 100 ns
	hal_timer_delay_usec(100);

	// Configure ADC
	for (k=0; k<ADC_DEFAULT_REGS_LENGTH; k++) {
		hal_adc_write_reg(adc_default_cfg_regs[k][0], adc_default_cfg_regs[k][1]);
		if (k==0)		hal_timer_delay_msec(50);
		else			hal_timer_delay_msec(30);
	}

	// Read back all registers
//	for (k=0; k<ADC_DEFAULT_REGS_LENGTH; k++) {
//		if (k==1 || k==2 || k==3 || k==12 || k==13 || k==20 ||
//			k==22 || k==23 || k==44 || k==45 || k==52 || k==53) {
//			hal_adc_write_reg(adc_default_cfg_regs[k][0], adc_default_cfg_regs[k][1]);
//		} else {
//			adc_regs[k] = hal_adc_read_reg(adc_default_cfg_regs[k][0]);
//		}
//	}

	// Get JESD PHY registers
	hal_pl_hw_get_jesd_phy();

	// Init PL JESD Rx Core
	hal_adc_init_pl_jesd();

	#if 1
		// Debug: Monitor JESD Interface
		hal_adc_jesd_monitor();
	#else
		// Trigger SYSREF for ADC/DAC JESD Interface
		//hal_lmk_trigger_sysref();
	#endif
}

//----------------------------------------------------------------------------
// Function Name		: hal_adc_init_gpio()
//
// Function Description	:
//
// Input Argument(s)	: No input
//
// Return Argument		: void
//----------------------------------------------------------------------------
void hal_adc_init_gpio(void) {

}

//----------------------------------------------------------------------------
// Function Name		: hal_adc_set_gpio_reset()
//
// Function Description	:
//
// Input Argument(s)	: No input
//
// Return Argument		: void
//----------------------------------------------------------------------------
void hal_adc_set_gpio_reset(u8 status) {

	// Active High Signal
	if (status == ENABLE)	hal_dbg_set_tps(HAL_DBG_TPS_ADC_IF_RESET);
	else					hal_dbg_reset_tps(HAL_DBG_TPS_ADC_IF_RESET);
}

//----------------------------------------------------------------------------
// Function Name		: hal_adc_set_gpio_sync()
//
// Function Description	:
//
// Input Argument(s)	: No input
//
// Return Argument		: void
//----------------------------------------------------------------------------
void hal_adc_set_gpio_sync(u8 status) {

	// Active Low Signal
	if (status == ENABLE)	hal_dbg_reset_tps(HAL_DBG_TPS_ADC_IF_SYNC);
	else					hal_dbg_set_tps(HAL_DBG_TPS_ADC_IF_SYNC);
}

//----------------------------------------------------------------------------
// Function Name		: hal_adc_set_gpio_pwr_dwn()
//
// Function Description	:
//
// Input Argument(s)	: No input
//
// Return Argument		: void
//----------------------------------------------------------------------------
void hal_adc_set_gpio_pwr_dwn(u8 status) {

	if (status == ENABLE)	hal_dbg_set_tps(HAL_DBG_TPS_ADC_IF_PDN);
	else					hal_dbg_reset_tps(HAL_DBG_TPS_ADC_IF_PDN);
}

//----------------------------------------------------------------------------
// Function Name		: hal_adc_read_reg()
//
// Function Description	:
//
// Input Argument(s)	: No input
//
// Return Argument		: void
//----------------------------------------------------------------------------
u8 hal_adc_read_reg(u16 reg_adr) {

	u8  buf[3];

	// Clear R/W field (b[15]=R/W)
	reg_adr &= 0x7FFF;

	// b[15]= R/W
	// b[14]= M - SPI Bank Access
	// b[13]= P - JESD page
	// b[12]= CH - Channel-A/B for JESD SPI

	// Set R/W field
	reg_adr |= 0x8000;

	// Set Tx buffer
	buf[0] = reg_adr >> 8;
	buf[1] = reg_adr & 0xFF;
	buf[2] = 0;

	// Start xmit
	hal_spi_send_data(adc_spi_handle, buf, buf, 3, HAL_SPI_BLOCK_DISABLE);

	return buf[2];
}

//----------------------------------------------------------------------------
// Function Name		: hal_adc_write_reg()
//
// Function Description	:
//
// Input Argument(s)	: No input
//
// Return Argument		: void
//----------------------------------------------------------------------------
void hal_adc_write_reg(u16 reg_adr, u8 reg_data) {

	u8  buf[3];

	// Clear R/W field (b[15]=R/W)
	reg_adr &= 0x7FFF;

	// b[15]= R/W
	// b[14]= M - SPI Bank Access
	// b[13]= P - JESD page
	// b[12]= CH - Channel-A/B for JESD SPI

	// Set Tx buffer
	buf[0] = reg_adr >> 8;
	buf[1] = reg_adr & 0xFF;
	buf[2] = reg_data;

	// Start xmit
	hal_spi_send_data(adc_spi_handle, buf, buf, 3, HAL_SPI_BLOCK_DISABLE);
}

//----------------------------------------------------------------------------
// Function Name		: hal_adc_init_pl_jesd()
//
// Function Description	:
//
// Input Argument(s)	: No input
//
// Return Argument		: void
//----------------------------------------------------------------------------
void hal_adc_init_pl_jesd(void) {

	u32 reg;

	// Reset JESD RX (b[0]=1-Reset in progress)
	hal_pl_write_reg(PL_JESD_RX_REG_RESET_ADR, 0x00010001);
	while (hal_pl_read_reg(PL_JESD_RX_REG_RESET_ADR) & 0x00000001) {}

	// Get JESD RX IP Version
	reg_jesd_rx[0] = hal_pl_read_reg(PL_JESD_RX_REG_VERSION_ADR);

	// Set ILA Support ([b0]=1-Enable)
	hal_pl_write_reg(PL_JESD_RX_REG_ILA_SUPPORT_ADR, 1);

	// Set SUBCLASS ([b1:b0]=1-Subclass1
	hal_pl_write_reg(PL_JESD_RX_REG_SUBCLASS_MODE_ADR, 1);

	// Set SYSREF ([b16]=1-Sysref Req on Resync, [b0]=1-Sysref Always)
	hal_pl_write_reg(PL_JESD_RX_REG_SYSREF_ADR, 0x00000000);

	// Set Test Mode ([b2:b0]=0-Normal)
	hal_pl_write_reg(PL_JESD_RX_REG_TEST_MODES_ADR, JESD_CORE_PRBSEL_NORMAL);
	//hal_pl_hw_set_jesd_rx_prbsel(JESD_PHY_PRBSEL_K28P5);

	// TODO: Set Rx Buffer Delay ([b12:b0]=-)
	//hal_pl_write_reg(PL_JESD_RX_REG_RX_BUF_DELAY_ADR, 6);

	// Set Error Report ([b8]=1-Enable Link Error Counter, [b0]=0-Enable Error Report using SYNC if)
	hal_pl_write_reg(PL_JESD_RX_REG_ERROR_REPORT_ADR, 0x0100);

	#if HW_CFG_ENABLE_ADC_LMFS_8224
		// Set Lanes In Use ([b4:b0]=7-8 Lanes)
		//reg = hal_pl_read_reg(PL_JESD_RX_REG_LANES_IN_USE_ADR);
		hal_pl_write_reg(PL_JESD_RX_REG_LANES_IN_USE_ADR, 0xFF);		// TODO: ?
		// Set Scrambling ([b0]=0-Disable Scrambling)
		hal_pl_write_reg(PL_JESD_RX_REG_SCRAMBLING_ADR, 0);
		// Set F = 2 ([b7:b0])
		hal_pl_write_reg(PL_JESD_RX_REG_OCTET_PER_FRAME_ADR, 1);
		// Set K = 16 ([b4:b0])
		hal_pl_write_reg(PL_JESD_RX_REG_FRAME_PER_MULTIFRAME_ADR, 15);

	#else
		// Set Lanes In Use ([b4:b0]=3-4 Lanes)
		hal_pl_write_reg(PL_JESD_RX_REG_LANES_IN_USE_ADR, 0xF);		// TODO: ?
		// Set Scrambling ([b0]=0-Disable Scrambling)
		hal_pl_write_reg(PL_JESD_RX_REG_SCRAMBLING_ADR, 0);
		// Set F = 1 ([b7:b0])
		hal_pl_write_reg(PL_JESD_RX_REG_OCTET_PER_FRAME_ADR, 0);
		// Set K = 32 ([b4:b0])
		hal_pl_write_reg(PL_JESD_RX_REG_FRAME_PER_MULTIFRAME_ADR, 31);
	#endif

	// Reset JESD RX (b[0]=1-Reset in progress)
	hal_pl_write_reg(PL_JESD_RX_REG_RESET_ADR, 0x00010001);
	while (hal_pl_read_reg(PL_JESD_RX_REG_RESET_ADR) & 0x00000001) {}
}

//----------------------------------------------------------------------------
// Function Name		: hal_adc_jesd_monitor()
//
// Function Description	:
//
// Input Argument(s)	: No input
//
// Return Argument		: void
//----------------------------------------------------------------------------
void hal_adc_jesd_monitor(void) {

	u32 base_adr;
	u8  k;
	u32 pl_rx_prbsel, pl_phy_prbsel;

	// Debug: Select test points
	hal_pl_hw_set_tps_1_mux(adc_tps_1);
	hal_pl_hw_set_tps_2_mux(adc_tps_2);
	hal_pl_hw_set_tps_3_mux(adc_tps_3);

	hal_adc_init_pl_jesd();
	pl_rx_prbsel = JESD_CORE_PRBSEL_NORMAL;
	pl_phy_prbsel = JESD_PHY_PRBSEL_NORMAL;

	// Get Sync Status (b[16]=1-Sysref Captured, b[0]=1-Link Sync)
	reg_jesd_rx[1] = hal_pl_read_reg(PL_JESD_RX_REG_SYNC_STATUS_ADR);

	// Trigger SYSREF for ADC/DAC JESD Interface
	hal_lmk_trigger_sysref();

	while (1) {
		// Get Sync Status (b[16]=1-Sysref Captured, b[0]:1-Link Sync)
		reg_jesd_rx[1] = hal_pl_read_reg(PL_JESD_RX_REG_SYNC_STATUS_ADR);

		// Get Link Error Status-1 (For Lane_0/7, [b31]=-, [b30]=-, [b29]=-, [b23:b21]/[b2:b0]= For Lane-7/0)
		// [b2]=1-Unexpected K, [b1]=1-Disparity Error, [b0]=1-Not in Table)
		reg_jesd_rx[2] = hal_pl_read_reg(PL_JESD_RX_REG_LINK_ERROR_STATUS_1_ADR);

		for (k=0; k<8; k++) {
			base_adr = PL_JESD_RX_REG_LANE0_CFG_BASE_ADR + 0x40 * k;
			// Get ILA CFG-0 Data of Lane-X (JESDV[b10:b8], SUBCLASS[b2:b0])
			reg_jesd_rx_lane[k][0] = hal_pl_read_reg((base_adr+PL_JESD_RX_REG_LANEX_ILA_CFG_DATA_0_OFFSET));
			// Get ILA CFG-1 Data of Lane-X (F[b7:b0])
			reg_jesd_rx_lane[k][1] = hal_pl_read_reg((base_adr+PL_JESD_RX_REG_LANEX_ILA_CFG_DATA_1_OFFSET));
			// Get ILA CFG-2 Data of Lane-X (K[b4:b0])
			reg_jesd_rx_lane[k][2] = hal_pl_read_reg((base_adr+PL_JESD_RX_REG_LANEX_ILA_CFG_DATA_2_OFFSET));
			// Get ILA CFG-3 Data of Lane-X (L[b28:b24],LID[b20:b16], BankID[b11:b8], DeviceID[b7:b0])
			reg_jesd_rx_lane[k][3] = hal_pl_read_reg((base_adr+PL_JESD_RX_REG_LANEX_ILA_CFG_DATA_3_OFFSET));
			// Get ILA CFG-4 Data of Lane-X (CS[b25:b24], N_PRIME[b20:b16], N[b12:b8], M[b7-b0])
			reg_jesd_rx_lane[k][4] = hal_pl_read_reg((base_adr+PL_JESD_RX_REG_LANEX_ILA_CFG_DATA_4_OFFSET));
			// Get ILA CFG-5 Data of Lane-X (CF[b28:b24], HD[b16], S[b12:b8])
			reg_jesd_rx_lane[k][5] = hal_pl_read_reg((base_adr+PL_JESD_RX_REG_LANEX_ILA_CFG_DATA_5_OFFSET));
			// Get ILA CFG-6 Data of Lane-X (RES2[b15:b8], RES1[b7:b0])
			reg_jesd_rx_lane[k][6] = hal_pl_read_reg((base_adr+PL_JESD_RX_REG_LANEX_ILA_CFG_DATA_6_OFFSET));
			// Get ILA CFG-7 Data of Lane-X (Subclass2 Only, ADJDIR[b16] PHADJ[b8], ADJCNT[b3:b0])
			reg_jesd_rx_lane[k][7] = hal_pl_read_reg((base_adr+PL_JESD_RX_REG_LANEX_ILA_CFG_DATA_7_OFFSET));
			// Get Test Mode Error count of Lane-X
			reg_jesd_rx_lane[k][8] = hal_pl_read_reg((base_adr+PL_JESD_RX_REG_LANEX_TEST_MODE_ERROR_COUNT_OFFSET));
			// Get Link Error count of Lane-X
			reg_jesd_rx_lane[k][9] = hal_pl_read_reg((base_adr+PL_JESD_RX_REG_LANEX_LINK_ERROR_COUNT_OFFSET));
			// Get Test Mode ILA count of Lane-X
			reg_jesd_rx_lane[k][10] = hal_pl_read_reg((base_adr+PL_JESD_RX_REG_LANEX_TEST_MODE_ILA_COUNT_OFFSET));
			// Get Test Mode MultiFrame count of Lane-X
			reg_jesd_rx_lane[k][11] = hal_pl_read_reg((base_adr+PL_JESD_RX_REG_LANEX_TEST_MODE_MF_COUNT_OFFSET));
			// TODO: Get Buffer Adjust (RX_BUFFER_ADJUST[b9:b0])
			reg_jesd_rx_lane[k][12] = hal_pl_read_reg((base_adr+PL_JESD_RX_REG_LANEX_BUFFER_ADJUST_OFFSET));
		}

		// Set Test Mode ([b2:b0]=0-Normal)
		hal_pl_write_reg(PL_JESD_RX_REG_TEST_MODES_ADR, pl_rx_prbsel);
		hal_pl_hw_set_jesd_rx_prbsel(pl_phy_prbsel);

		// Debug: Select test points
		hal_pl_hw_set_tps_1_mux(adc_tps_1);
		hal_pl_hw_set_tps_2_mux(adc_tps_2);
		hal_pl_hw_set_tps_3_mux(adc_tps_3);
	}
}

over 5 years ago

0 Brian2001 over 5 years ago

TI__Intellectual 2750 points

Hello Taylan,
I have sent this to an engineer that works with the ADS54J40
Regards,
Brian

0 TAYLAN ERTAŞ over 5 years ago in reply to Brian2001

Prodigy 100 points

Hi Brian,

Is there any progress on this problem?

Do you observe similar results?

0 jim s over 5 years ago in reply to TAYLAN ERTAŞ

TI__Guru* 91947 points

Taylan,

Sorry for not getting back sooner. You have a couple of register writes that are either wrong, missing or invalid. See the attached files for correct register settings. I have also attached a chipscope view of the ILA data captured from all 8 lanes using the TI EVM. You will see that every lane has a unique ID. Are you issuing a hard reset to the ADC after power and clocks are applied? Are you following the ADC required power sequencing per the data sheet in section 10.1?

Regards,

Jim

adc_lmfs_4211_te_new.cfg ADS54J40_LMF_8224_te_new.cfg 6242.ILA example LMFS_8244.pptx

0 jim s over 5 years ago in reply to jim s

TI__Guru* 91947 points

Taylan,

Are you still having issues with this? If not, I would like to close this post.

Regards,

Jim

Data converters

Data converters forum

ADS54J40: ADS54J40 JESD204B Link Setup Failure