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ADS4242: Phase difference between 1ch and 2ch

Jeffrey
Expert 1920 points
Part Number: ADS4242
Other Parts Discussed in Thread: TMS320C6748

Hi, 

We are testing the high-speed signal processing application as ADS4242 + TMS320C6748(upp port).

But there is the phase difference between 1ch and 2ch of ADS4242 at 4.096MHz sampling rate, 5kHz input frequency.

The phase difference is from 0.48-degree to 0.9-degree, it's like delaying or omitting the output clock(1-clock to 2-clock),

and all data(1ch/2ch), sampling frequency are no problem.

What's a root cause of this problem?

Is the sampling of 1ch and 2ch implemented at the same time, simultaneously?

If yes, share me with the detailed document.

Please refer to the bellow schematics.

ADS4242_schematic.pdf

TMS320C6748_schematic.pdf

Regards,

Jeffrey

  • 0
    TI__Genius 12780 points
    Hi Jeffrey,

    We are taking a closer look at your question, and will be back with you soon.

    Best Regards,

    Dan
  • 0 in reply to dBrock
    Expert 1920 points
    Hi Daniel,

    Thanks for your response.
    We're sorry but we hope you answer the questions as soon as possible.

    Regards,
    Jeffrey
  • 0 in reply to Jeffrey
    TI__Guru* 91947 points

    Jeffrey,

    Do you see any type of phase difference when placing both channels in ramp pattern test mode? Do you have an option to swap the two analog input sources to see if the offset follows the source? If you are using serial SPI interface, can you send your register settings? Is it possible to only use one of the two ADC_CLK_OUT inputs on the FPGA to clock in both data buses. There may be a delay issue between these two inputs. There also may be some reflections going here as I cannot see how these traces are routed. Do you see this phase difference when running with a slower sample rate? I cannot see how the two analog signals are sourced from. Can you send the schematic portion of this?

    Regards,

    Jim 

  • 0 in reply to jim s
    Expert 1920 points
    Hi Jim,

    Thanks for your comment.
    We'll check and test like your comment, and then let you know that.

    Regards,
    Jeffrey
  • 0 in reply to jim s
    Expert 1920 points
    Hi Jim,

    In short, we want to know just two things.
    1. Is the sampling of 1ch and 2ch implemented at the same time, simultaneously?
    2. Is there the output difference or offset or delay between 1ch and 2ch of ADC?
    Can you answer me about that?
    If you have a detailed document, please share me with it.

    Regards,
    Jeffrey
  • 0
    TI__Guru* 91947 points

    Jeff,

    Both channels sample simultaneously. There will be a small delay due to the routing of the clock between the ADC's in the package, but this would be very minor.

    Are you saying the data from one channel is 1 to 2 clocks late/early from the other channel? Do you see this if you place the part in ramp test pattern mode? 

    You did not send the full analog input chain. Are the inputs routed exactly the same length? Did you verify with a dual channel scope both channel inputs are identical at the ADC input pins? 

    Are you programming the part using serial or parallel SPI mode? If serial, can you send your register settings? Do you always issue a reset after power up? Are you setting both channels to low speed mode and disabling high frequency mode?

    Regards,

    Jim

  • 0 in reply to jim s
    Expert 1920 points
    Hi Jim,

    Thanks for your answer.
    What we want to know is just 2 things(simultaneous sampling and output difference/offset/delay) like above comment.
    We understood that.
    We are going to verify DSP for resolving this problem instead of ADC.
    Thanks.

    Regards,
    Jeffrey
  • 0 in reply to Jeffrey
    TI__Guru* 91947 points

    Jeffrey,

    The ADC samples both channels simultaneously.

    There are two indepenant mechanism which may result in phase difference in digital output of two channels even if they sampled same input.

    1. Aperture delay:

    As specified in datasheet, typical aperture delay between two channels of a given device is +/-70ps.

    This means, if a frequency ‘fin’ is sampled by two channels, the digital output can typically have a phase difference of +/- 2*pi*fin* 70ps.

    1. Bandwidth mismatch:

    The sampling network (external and internal) of two channels can have different bandwidth. The mismatch among internal network can be as high as +/-15%.

    For a single pole network, tan-1(win/wo1) – tan-1(win/wo2) is the phase difference.

    Regards,

    Jim

  • 0 in reply to jim s
    TI__Guru* 81715 points
    Keeping the DSP thread cross linked - have not been able to find anything specifically wrong - and would like to make sure that the questions asked here by jim are duly addressed

    e2e.ti.com/.../2675183
  • 0 in reply to jim s
    Expert 1920 points
    Hi Jim,

    Thanks for your explanation.
    We understood the two independant mechanism you explained.
    Thanks.

    Regards,
    Jeffrey