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ADS1209: tD2 and tD3 timing

Part Number: ADS1209

Hello,

Could you tell me the uncertainty of the values tD2 and tD3 for the ADS1209 with CLKSEL = 0?

For tD2 the datasheet only gives a max values of 10 ns. How low can this value be?

For tD3 the datasheet only gives a min values of t3 + 7ns. Assuming no uncertainty on t3, how high can this value be?

Best regards

Rémi Freiche

  • Hi Remi,

    Thanks for your post and welcome to the forum!

    Since it is not spec'd in the datasheet I cannot say exactly how low tD2 can be or how high tD3 can be, but I would say that the average time is most likely close to their max and min values respectively.

    What are you trying to do that requires timing characteristics that are this specific?
  • Because of crosstalk issue in my transmission cable, I would like to work without using the CLKOUT signal on the ADS1209. Instead I would like to reuse the CLKIN signal generated on my control board (initialy for the modulation on the ADS1209) for the delta sigma filtering. This works pretty well however I need to now what is the tolerence on the delay between CLKIN and DATA on the ADS1209, to make sure that my clock and data are correctly synchronised when filtering in any case.

    Do you have any way to give me a value here? What I am looking here is more or less the skew between CLKIN and DATA?
  • Thank you for the clarification. Interesting issue and an excellent idea to fix it.

    One small thing that I noticed from the OP is that tD3 = t2 +7ns, not t3 +7ns.

    The skew between CLKIN and DATA will be tD2 + tD3. As an example, if you're using the minimum CLKIN period of 41.6ns with a 50% duty cycle:

    t2 = 20.8ns
    tD3 = 20.8ns + 7ns = 27.8ns
    tD2 = 10ns MAX

    This gives you a range of 27.8ns to 37.8ns. A value of 0ns for tD2 sounds very optimistic to me, so I would probably experiment in the 30-35ns range to start.

    Unfortunately, I can really only speculate. I recommend testing under your specific conditions to get a more reliable answer. Do you believe that writing code based upon static timing values could lead to issues over time? Are you interested in reading every single time data is ready or is this for more of a periodic check?
  • Thank you for your answer. I think there is still a bit of misunderstanding here.

    I already tested this solution will success. However I need to be sure that it will work accross of the temprature range and with different ADS1209 batch. Finaly my issue is not really the propagation delay, but the uncertainty on the propagation delay. (This is what I call Skew but maybe it's not the right word). Experimenting will not give me more answer since the test will only be done on one OP.

    Therefore since the delay between CLKIN and DATA will be tD2 + tD3, I can say that the maximum uncertainty on the delay for tD2 is 10ns but I do not know what is the maximum uncertainty on the delay for tD3. Therefore I cannot garantee my design.

    Is there any way to get a value for this? maybe from the intern circuit? It does not have to be extremely precise, i just need a maximal value.

    Rémi Freiche

  • Hi Remi,

    I understand and agree with you that this creates a challenge. There are periods in the timing diagram that cannot be reliably measured without CLKOUT which makes it difficult to put together a guaranteed solution. Unfortunately I cannot provide a maximum value for tD3 time.

    Are you using an FPGA or DSP? Is it possible for you to sense the second rising clock edge after start?

    If so, you can capture data during tH1. Please see the diagram below:

    Purple is your start.

    Green is the second rising CLK edge after start.

    Red shows tD2, 0-10ns from green to red.

    Blue shows tH1, (t2-3) which is 17.8nS from red to blue if we're using the minimum clock period of 41.6nS and assuming a 50% duty cycle. 

    Will your cables have varying lengths and what is the time delay/meter? Is 17nS a large enough window to capture the data in your system?