• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 46 subscribers
  • Views 606 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS7822: Wrong data output

Kuramochi Tadahiko
Guru 28715 points
Part Number: ADS7822

Hi,

Wrong data output is observed on my customer's circuit as attached.

7127.ADS7822.xlsx

"Wrong" means below;

1. DOUT goes low at the same time as falling down of first CLK.

2. The outputted data is all "0" regardless of input voltage.

This symptom is usually seen with multiple samples.

Why is this symptom occurred?

Best Regards,

Kuramochi

  • 0
    TI__Mastermind 24940 points
    Hello,
    This definitly not correct behavior. Thank you for providing the scope shots, there does not seem to be any timing errors
    Would you ask the customer to try these two test:
    Ask them to change the clock's idle voltage from high to low; although the idle time does not matter, it affects the starting point of the clock cycles.
    Also, would you ask them to increase the number of clock cycles. From the scop shot it looks like they might be short, the ADC needs 16 clock cycles and this will ensure that all needed clocks are provided
    Regards
    Cynthia
  • 0 in reply to Cynthia
    Guru 28715 points

    Cynthia-san

    Thank you for your advice.

    >Ask them to change the clock's idle voltage from high to low

    Is  the clock's idle voltage below inside of red rectangle?

    > the ADC needs 16 clock cycles and this will ensure that all needed clocks are provided

    Is this restriction mentioned on the datasheet?

    Best Regards,

    Kuramochi

  • 0 in reply to Kuramochi Tadahiko
    TI__Mastermind 24940 points

    Kuramochi-san,

    Correct, the idle voltage is in the red box. this is the voltage that the clock is at at in between cycles.

    The timing specifications are given in Table1 which reference Figure 22, shown below. The table gives a minimum of 16 clock cycles for the cycle time, this is why I ask to try increasing the number of clock cycles.

    Regards

    Cynthia