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ADS8332: Quiet Zone

Part Number: ADS8332


I am currently interfacing the ADS8832 and am wondering how to best go about it.

In "9.5.4 Reading the Conversion Result" the datasheet states "The conversion result is available to the input of the output data register (ODR) at EOC and presented to the output of the output register at the next falling edge of FS/!CS.The host processor can then shift the data out through the SDO pin at any time except during the quiet zone. This  duration is 20 ns before and 20 ns after the end of sampling (EOS) period."

Does this mean, that it is mandatory to sync the SPI transfer to the EOC? What happens if a SPI transfer is timed so that it collides with the quiet zone?

With kind regard

  • Hi Simon,

    You do need to meet the setup/hold times of /CS relative to the EOC signal; these are specified in Section 8.7 and 8.8 of the datasheet. If you violate these timing requirements, you could get bad/random data. So yes, in this respect, the SPI transfer must be synced to the EOC.

    The quiet zone is a bit different; this is relative to the /CONVST line going low in manual trigger mode (or 3 CCLK's after EOC in auto trigger). In this case, you do not want to clock data out of the device during this time period, or you could increase the noise in the reading results. This quiet zone is the time period when the input sampling capacitor is settling to the last LSB's of the input voltage, and is most sensitive to any digital noise.

    In any case, try to follow one of the clocking examples in the datasheet, such as Figure 1 or Figure 2, to ensure best performance of the device.

    Keith N.
    Precision ADC Applications
  • Hello Keith,

    thank you very much for your reply!

    I am reading the ADS8332 from a Linux system and am not able to strictly adhere to the clocking examples.

    If I only want to take a single reading from the auto triggering ADC, am I save to clock it out at an arbitrary point in time, as a possible violation of the quiet zone would only affect the ongoing conversion but not the data being clocked out to SDO?

    The question arises as I'm not quite sure how to interpret "made available" and "presented" in section 9.5.1:" The internal data register content, which is made available to the output register at the end of conversion, is presented on the SDO output pin on the falling edge of FS/!CS.".

    If the output register is able to change while !CS is low the SPI master could receive data composed of conversions from different samples where the LSBs are unnecessary noisy once a (slow) SPI transfer takes place at the wrong point in time.

    With kind regards,


  • Hello Simon,

    In order to get valid data, you must meet the timing requirements. The easiest way to meet these would be to use the manual trigger mode, and issue a /CONVST. (This could be done with a GPIO.) After the falling edge of /CONVST, if you wait 2uS, you can then pull /CS low and clock the data out. After clocking the data, you can then issue another /CONVST pulse to start the next conversion. You will not get the maximum sampling rate, but this is an easy way to guarantee valid readings.

    By setting the ADS8332 into auto-trigger, and reading data at an arbitrary time, at some point, you will violate the setup/hold times of the /CS pin. If /CS falls within the window of EOC rising, you could get completely random data for the reading. The rising edge of EOC is the moment when the internal data conversion result is presented, or settling, to the inputs of the output register. If this data is not settled, then latching this unsettled data into the output register by pulling /CS low will give random results.

    The percentage of random data, or noise, in your conversion results will depend on how often you fall in this window. It may only occur very infrequently, and you could simply ignore these reading 'excursions', or it could occur at a high enough rate to completely corrupt the signal that you are trying to measure.

    I hope this helps!
    Keith N.