Hi TI‘s expert,
Currently I am designing a deserializer for DDC2256A and Xilinx Zynq-7000. The inputs for deserializer are standard: DCLK, FCLK and DATA are outputs of ADC and CONV is generated inside FPGA. The output of the deseriazer should be implemented as a master AXI stream interface. The output data of deserializer should contain ADC data (with all headers and tails), clock counter and frame counter. So for each frame one should have 256*3 (ADC data) + 4*2 (headers) + 2*2 (tails) + 4 (clock counter) + 4 (frame counter) = 788 bytes of data. Are there any reference design for such deserializer (preferably in Verilog)?
May be I am asking a dump question but I am not very experienced in Verilog and FPGA programming.
Best regards,
Mikhail.
