Hi Jones,
The ADS7865 multiplexer is controlled by writing the CONFIG register, bits C1, C0. The device supports a maximum sampling rate of 2-MSPS, with a maximum external CLOCK frequency of 32MHz. It takes a total of 16 CLKs per frame to cycle through a conversion result, (i.e. the minimum conversion cycle of 0.5us, or 2-MSPS maximum sampling rate).
Looking at the timing diagram below, the multiplexer updates on the rising edge of WR input, after the CONFIG register is written on DB[11:0]. The configuration register is described on Table 4, p.17 of the datasheet.
Therefore, the time delay between the mux changes is dependent on your CLOCK frequency and interface timing, as shown on figure 32 below. At maximum sampling rate, the MUX updates every 0.5us.
Please let me know if you have any questions,
Kind Regards,
Luis Chioye
