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ADS42JB49EVM: SYNC~ not asserted

Yogitha Rajasekhar
Intellectual 290 points
Part Number: ADS42JB49EVM
Other Parts Discussed in Thread: ADS42JB49

Hi,

I have interfaced ADS42JB49EVM, TSW14J10 and KC705. ADC sampling clock is 156.25MHz, line rate of 3.125Gbps and LMF_221.

At any time I am going to drive only channel A inputs. 20x mode states that one lane per ADC will be active. So, even if only one channel is active are both ADC functional ? How do I disable the unused lanes in 20x mode and know which of them are active (DA0/DA1 and DB0/DB1 to connect to FPGA side rx pins).

Though sysref is captured on FPGA side I do not get link synchronized. I have inserted the configuration file. ADS42JB49_221.cfgHow do I proceed in debugging.

Thanks,

Yogitha

  • 0
    TI__Mastermind 44530 points
    Hi Yogitha
    I have notified the ADS42JB49EVM expert regarding your question. You should receive a more detailed response soon.
    Best regards,
    Jim B
  • 0
    TI__Guru* 91947 points

    Yogitha,

    The LMF setting of 221 is not a valid setting for this part. The only settings that are valid are 421 and 222.When using the TSW14J10EVM and KC705, please use the attached config file for the ADC. This will disable the unused lanes.

    Regards,

    Jim

    ADS42JB49_EVM_LMF222_150M_KC705.cfg

  • 0 in reply to jim s
    Intellectual 290 points

    Hi JIm,

    I will change the settings to 222 mode. I want to configure the ADC for 156.25 MSPS and 3.125Gbps line rate. The configuration file you shared is for 150 MSPS. Can you please share config file for 156.25 MSPS and LMF_222.

    From the FPGA side, I need to know where to connect my rx lanes on to the ADC EVM. Do you mean that I can connect to any of the four lanes and the rest two will be disabled automatically

    Thanks,

    Yogitha

  • 0 in reply to Yogitha Rajasekhar
    TI__Guru* 91947 points

    ADS42JB49_LMF_222_KC705.pptADS42JB49_EVM_LMF222_156p25M_KC705.cfgYogitha,

    In the FPGA, you will be using the balls E4/E3 for lane 0, which goes to FMC pins C6/C7 and balls B6/B5 for lane 1 which go to FMC pins A6/A7. These are the two lanes used by the ADC (DA0 and DB0) output which map to FMC pins C6/C7 and A6/A7. The unused lanes will be automatically disabled.

    I ran this setup on our hardware using existing configuration files. The procedure is attached. I then saved the new configuration file and have attached that as well.

    Regards,

    Jim

  • 0 in reply to jim s
    Intellectual 290 points

    Hi Jim,

    Thanks for the help. I was able to get the link established. 

    After receiving K characters, SYNC is de-asserted. But I see that SYNC is not stable and is toggling. Internal debug registers of JESD RX in FPGA, shows that unexpected K characters are received error set. JESD RX doesn't output any data in this case.
    I tried disabling ILA on both sides, SYNC is still toggling but I get some data out of JESD RX. What could possibly cause this.

    Thanks,

    Yogitha

  • 0 in reply to Yogitha Rajasekhar
    TI__Guru* 91947 points

    Yogitha,

    This could be caused by several things. Is your "K" value the same in both the ADC and FPGA? Is K x F > 17 per the standard? What is your SYSREF frequency? if your FPGA is using a reference clock and core clock, one of these may be set to the wrong frequency. Can you ignore ILA errors in your FPGA code? These errors will cause SYNC to toggle. If this is the case, you can debug this later after the link is stable.

    Regards,

    Jim

  • 0 in reply to jim s
    Intellectual 290 points

    Hi Jim,

    I have set K value to 32. The configuration file you shared had sysref divider set to 480. Do I need to set the sysref freq to multiple of LMFC period even if it is configured as sysref pulses. Should I use sysref as continuous clock or as pulses?

    The ref clock and core clock are configured as 312.5MHz for line rate of 3.125GHz.

    -Yogitha 

  • 0 in reply to Yogitha Rajasekhar
    Intellectual 290 points

    Hi Jim,

    I have got SYNC stable after changing the core clock freq

    In the TSW14J10 EVM user guide, it is mentioned that for line rate between 1G and 3.2G, the core clock and ref clock for FPGA needs to be lane_rate/10 which is 312.5MHz for 3.125Gbps lane rate. With this settings I got SYNC toggling. 

    After changing the core clock freq to lane_rate/40 (78.125MHz), the link is stable.

    Can you explain the considerations to have SYREF continuous or as pulses.

    Thanks,

    Yogitha

  • 0 in reply to Yogitha Rajasekhar
    TI__Guru* 91947 points

    Yogitha,

    SYSREF can either be continuous, pulsed, or turned off after the link is established.  Most customers would turn it off as this input adds noise to the data. If you do disable SYSREF, make sure it is not floating as it could cause a false pulse to occur, which could cause the link to go down. If the link does goes down for some reason, you will have to turn it back on or pulse it to get the link re-established. 

    Regards,

    Jim