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DAC38RF93: the seting of register

Part Number: DAC38RF93

Hello、I  get some problem to be resolved when using DAC38RF93.

1,when i using the DAC PLL, the reference frequence is 500MHz,PLL-N=1,pll_m=5, I choose the LOW VCO, I want to know the value of pll_vco value I shoud set if I need the VCO out put frequecy is 6G?

2, In the datesheet PAGE 141, the figure 167 tell us we can not operate the register until we we get the bit [15 : 11]=10000 by reading the register address "7F",however the alue i get is always"000000". I ignore about this step and still configure the register,i seems that the date can be written into the register i need. So, I doute is there any problem?

3, the sample rate i use is 3Ghz,  84111 with 2 TX, dual DAC with signle link ,the actual state i want the two DAC cahnnel work independently, rx 0-3 for DACA and rx4-7 for DACB, THE FOLLOWING SEQUENCE  IS REGISTER I SET:

09:0003   0A:0610     OC:26A0   0D:8001 19:0001  20:4CCC  1F:CCCC  1E:CCCD  25:6600  27:1144   28:0440  09:0001  4A:0F03  09:0002  4A:F003  09:0003 4B:1300  4C:1303  4D:0100   4E:0F4F

In the FPGA  ,i set THE  L=8, F=1,K=20,THE frequecy of the sysref is 3.125M

but  I can not get the SYNC signal high. is there any problem in my setting.

thank you!

  • Hi,

    If you are using your own board and not TI EVM, you can use the DAC38RF93 GUI in simulation mode to generate and save a config file that you can use to configure your board. Also, before testing the DAC with an FPGA, enable the constant data and NCO inside DAC to output a sine wave. If this works, it will confrm the DAC has been configured correctly. The steps to enable constant data and output a 100MHz sine wave from DAC A are as follows:
    1)Page 1, address 0x2F, bit0 = 1 //enable consant data
    2)Page 1, address 0x30 = 0x3FFF //set the constant value
    3)Page1, address 0x0C=0x2622 //Enable mixer and NCO on Path AB
    4)Page1, address 0x1E=0x4444
    Page1 address 0x1F=0x4444
    Page1 address 0x20=0x0444 //set NCO frequency to 100MHz assuming 6GHz clock
    5) Page1, address 0x28, bit1 = 1
    Page1, address 0x28, bit1 = 0//Toggle SIF SYNC

  • Thanks for your reply.Can you show me the link of the DAC38RF93 GUI, I HAVE try to find , but faild. thank you very much
  • Thanks for you suggestion. I have download the GUI software name"slac722a", and i do not have the TI EVM . The software can not be open. Can you show me the register value of my design where my working parameters is as follows:
    reference clk:500M, PLL enable, sample clock=6G, dual DAC,1 IQ pairs, 4 lane ,12 interpolation,LMFSHD:84111
    THANK YOU very much!
  • Hi,

    The configuration file for "500M, PLL enable, sample clock=6G, dual DAC,1 IQ pairs, 4 lane ,12 interpolation,LMFSHD:84111" is attached




  • Thans for your reply. In the configuration file,
    the page4 :
    0x3b = 0x9002
    0x3c =0x8029
    0x3e =0x0929
    we can get to known that MPY=0x14,RATE=01,SERDES_CLK_SEL=1,SERDES_REFCLK_DIV=2. So I have some question:
    1,The table 4 is not have MPY=0X14, can you explain the relationship between lane rate and effect when MPY=0x14?
    2, rate=01,so pll output frequency=0.5*line rate. In the system as described above, the line rate is 5Gbps, so pll output frequency is 2.5G, how to calculate the relationship between DAC PLL output and SERDES PLL output?
  • Hi)

    1) I have attached an updated table. This will also be corrected in the next revision of datasheet.


    SERDES_REFCLK_DIV is programmed through register 0x3B, bits 14:11



  • Thanks for your reply. I want to know if there are any other difference between the newest version and the old version published on the internet. Can you send me the next version of the datesheet with the miastakes have be corrected! Thank you!
  • Hi,

    I am not aware of any other changes currently but all changes we make will be well documented.

  • Can you explain the register page 4,0x0a. some clock, such as full rate, quarter rate, havs been mentioned in this register, can you explain me the useage and the relationship between these clock and sample clock or serdes clock?

  • Hi,

    These clocks are used to handover data from digital to the analog blocks. Extra details cannot be made public.
    Please open a new thread if you have to ask another question that is not related to your original question.