Hello,
In Digital specifications of ADC3341, it is written that digital inputs of ADC3441 (RESET, SCLK, SDATA, SEN, PDN) support 1.8V and 3.3V logic levels, but why not 2.5V?
My question is I have an FPGA with 2.5V logic levels, could I connect FPGA IO to ADC directly IO without level shifter?