Hello,
I am trying to use the DAC7654 with an FPGA that creates the signals for the serial interface of the DAC. My signals from the FPGA are LVCMOS33 and through the wiring from FPGA to the evalboard (which hosts the DAC7654) I have some signal reflections/capacitances, that I cannot avoid entirely. For example: The serial data clock runs at 50ns period and 50% duty cycle and has a voltage over and undershoot. The magnitude of this over and undershoot can be up to 800mV, with careful tuning I can get it down to 600mV. For this I have a question:
Will I damage the DAC with this behaviour? Are the maximum ratings in the data-sheet for DC voltages or VRMS or peek-voltages? (E.g. the maximum ratings specifications define a minimal voltage of -0.3V)
Cheers Uwe
