We have a design using the ADS5474-SP clocked at 125MHz. As the datasheet is spec’d at 250MHz we are working through how this effects a lot of the timing in the system.
We understand that (assuming a 50/50 duty cycle) the data valid window of Tsu+Th = 1.5+.9nS = 2.4nS in reference to a 250MHz clock will grow by 4nS … i.e. 1.5 + .9 + 4 = 6.4nS.
Our question is will this new 4nS of ‘growth’ show up all on the hold side of the DRY rising edge (new Tsu=1.5+0=1.5nS, new Th=0.9+4=4.9nS) , or be equally split between the setup side and hold side (new Tsu=1.5+2=3.5nS, new Th=0.9+2=2.9nS)? I think the answer is equally split. Can you confirm?
Thanks for your Help!