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ADS1257: Single-Cycle settled conversion

Part Number: ADS1257

Hi,

Let me ask you a question about "Single cycle" .

There is a description on the datasheet as below. (Red)

Does this mean "Single-Shot Mode", right?

I do not understand why is "<= 1000SPS".

Will you tell me why is "1000SPS"?

Thanks for your support.

Best Regards,

  • Hi Takumi-san,

    The ADS1257's digital filter is made up of a SINC5 filter and a programmable averager (SINC1) in series, as shown below:

    Notice that the data is decimated and the output rate at each stage gets progressively smaller.

    For slower data rates (higher number of averages), the majority of the digital filter's settling time is required by the programmable averager (SINC1) filter, and the digital filter is said to settle within a single-cycle (one conversion period).

    At higher data rates (lower number of averages), the majority of the settling time comes from the SINC5 filter, which takes roughly five conversion periods to settle since this is a higher-order filter than the SINC1 programmable averager.

    For this reason, the ADS1257 datasheet specifies that conversions are only single-cycle settling for data rates <= 1000 kSPS.

    For additional details on SINC filters, please refer to this blog post:

    Best regards,
    Chris

  • Hi Chris-san,

    Thank you very much for your kind explanation.

    I understood about SINC filter.

    But sorry, I still do not understand well about settling time...

    Please check the Table12, datasheet 30page, as below.

    According to this table, in case of 1000SPS, the settling time is 1.18mSec > 1mSec.

    So I suppose that it seems to be better to say "Single-Cycle Settled Conversions" means "<= around 500".

    Will you advise me what is not correct of my idea?

    Thank you in advance.

    Best Regards,

  • Hi Takumi-san,

    Certainly, I will try to explain further...

    It is very for the first conversion result to be delayed, we call this is the "settling time". This is due to additional digital delays in the data path, including any delay time from the start signal to start of conversion, the digital filter calculation, the math operations associated with calibration calculations, and the time to set /DRDY low. All of these delays summed will exceed the conversion period (1 / data rate).

    For the first conversion there is no way to mask (hide) the extra delays; however, for all on-going conversions many of these delays occur in parallel (similar to a pipelined processor) such that the digital filter calculation becomes the only perceived delay. The (SINC1) digital filter settling time is single-cycling since if you applied a step input at the beginning of a conversion period you would have settled data in the next conversion. Therefore, the filter delay is technically a single conversion period (or cycle); however as you pointed out, the first conversion itself is slightly delayed and does not appear to settle within a single-cycle.

    The term "single-cycle settling" is probably not the best term to precisely describe the behavior you would expect, but it has caught on as a common term in the industry and this behavior is consistent for most every delta-sigma ADC with a digital filter.

    Best regards,
    Chris