• State TI Thinks Resolved
  • Locked Locked
  • Replies 6 replies
  • Answers 2 answers
  • Subscribers 47 subscribers
  • Views 529 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADC3224: ADC usage in syncronous sampling

user542656
Prodigy 20 points
Part Number: ADC3224

Hello, 

SYSREF function and usage is not explained in datasheet.

So when and how I supposed to use it?

Who aperture delay varies over temperature +20..+50C. And how delay variation over temperature between parts behave?

I expect that aperture delay is somewhat constant for channel so I could make factory calibration.

BR, Timo

  • 0
    TI__Genius 12780 points
    Hi Timo,

    I am taking a closer look into your questions, and will be back with you soon.

    Best Regards,

    Dan
  • 0 in reply to dBrock
    TI__Genius 12780 points

    Hi Timo,

    I have contacted the design team in order get the information you have requested. Thank you for your patience!

    Best Regards,

    Dan

  • 0 in reply to dBrock
    Prodigy 10 points

    I just did a google search for sysclk adc3224 and found this thread. I'm awaiting the answers. The datasheet and EVM user's guide really should be updated with whatever information you can provide.

    They have a setup and hold time, so I can infer that sysref is supposed to be a synchronous logic signal, not a clock, but there are no timing diagrams, theory of operation write-up, or examples. I suppose I'd guess that it's a single cycle wide pulse, active high and has some unspecified but fixed timing relationship with the start of the FCLK output.

    It's not at all clear what would happen if I put a 50% duty cycle frame signal on there, or if I changed it on the fly what would happen to the samples in transit... not that I would... :-)

    Nick

  • 0 in reply to Nicholas Dietz
    TI__Genius 12780 points

    Hi Timo and Nick,

    The SYSREF is used to synchronize/reset the internal clock divider. This allows for multiple device synchronization. Page 17 of the data sheet states the SYSREF voltage levels and the required setup and hold time with respect to the sampling clock.

    With regard to the aperture jitter, aperture delay between two devices can be expected to be +/- 200 ps across temperature.

    Best Regards,

    Dan

  • 0 in reply to dBrock
    Prodigy 20 points

    Ok, so sysref is pulse with 1ns setup time before CLK and 0,1ns hold time. this is now clear.

    yes I can see that delay varies +-200ps, but I'm interested how it varies in my narrow temp range +20..+50C. can I expect it to be linear +-20ps or someting else.

    BR, Timo 

  • 0 in reply to user542656
    TI__Genius 12780 points
    Hi Timo,

    The main driver of difference for the aperture jitter between different parts is the process variation, so it would be difficult to be precise in this measurement.

    Coming back to the datasheet, there is +- 150 ps of aperture delay between two units at the same temp and supply voltage. A change of +- 20ps over your temperature range is a fair assumption.

    Best Regards,

    Dan