DAC5652A: Clock signal accept after SLEEP mode

Naokiu,

We are looking into this.

Regards,

Jim

Naoki,

With the clock already present to the DAC, after sleep goes from high to low, the output was valid after one clock cycle.

Regards,

Jim

Hello Jim,

Thank you for your reply.

Sorry for my poor explanation.

I attach the file that written the question.

DAC5652A_sleep_to_clock.pptx

Could you tell me the answer?

Best Regards,

Naoki Aoyama

Naoki,

One thing I forgot to point out is the clock shown in the photo is actually an inverted version of the clock going to the DAC.

Regards,

Jim

Naoki,

I sent a sign wave but it was in two's complement format instead of unsigned binary.

Jim