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DAC7716: Output voltage shifted after applying only AVDD and AVSS

Part Number: DAC7716

Hi support team,

Regarding power supply of DAC7716, is there a possibility of destruction of the IC when applying voltage as follows?
· AVDD - AGND : +15 V
· AVSS - AGND : -15 V
· DVDD-DGND : No supply (Normally added +5 V)
· IOVDD - DGND : No supply (Normally added +5 V)
· REF-A - REFGNDA : No supply (Normally added +3.3 V)
· REF-B - REFGNDB : No supply (Normally added +2.5 V)
* Voltage references (+3.3 V and +2.5 V) are generated from +5 V power supply

On the customer's board, when the power supply (+5 V) of DVDD and IOVDD was turned on and off several times while applying the power supply (±15 V) of AVDD-AGND and AVSS-AGND, the output voltage of only one channel shifted lower (about 0.4 V lower than the expected value).
What is the possible reason for the output voltage shift?

Sincerely,
M. Tachibana

  • Hello,

    The power-supply sequence prescribed in the datasheet should be followed. Any time a datasheet indicates a recommended sequence, this is the case.

    Generally speaking the internal OTP memory is powered on the digital domain (DVDD). If the digital rail is not powered when the analog supply ramp crosses the comparator threshold to trigger OTP reads, the analog circuits will effectively load invalid OTP memory values which can corrupt trim coefficients and other device parameters.

    I don't totally follow exactly what happened in your second paragraph case, but one potential is that the offset error trim values were not loaded correctly due to this sequencing and this is what has lead to unexpected offset on the channel you have described.
  • Hi Duke-san,

    I understood the possibility that the output voltage may become abnormal unless the IC is started up according to the power supply sequence described in the data sheet.
    However, the customer says that even if the IC is started up according to the power supply sequence, the output voltage of only one channel is shifted by 0.4 V (the expected voltage is about -2.0V and the actual output voltage is about -1.6 V).

    As a worst case scenario test, the customer turned on and off the power supply (+5 V) of DVDD and IOVDD several times while applying the power supply (±15 V) of AVDD-AGND and AVSS-AGND.
    After that, the output voltage of a certain channel will remain abnormal even if the IC is started up by normal power supply sequence.

    The customer thinks that the IC was broken because power supply had been applied as below.
    · AVDD - AGND: +15 V
    · AVSS - AGND: -15 V
    · DVDD-DGND: No supply (Normally added + 5 V)
    · IOVDD - DGND: No supply (Normally added + 5 V)
    · REF-A - REFGNDA: No supply (Normally added + 3.3 V)
    REF-B - REFGNDB: No supply (Normally added + 2.5 V)

    Although I think it does not exceed the absolute maximum rating, is there any possibility that the IC will be destructed?

    Sincerely,
    M. Tachibana
  • Techibana-san,

    I would agree that the specific sequence described with only AVDD and AVSS provided to the device should not permanently damage a device.

    Can you share a schematic for this design? What is the exact expected output range? I would like to understand if / how they are using the user calibration registers.
  • Techibana-san,

    Any response to my previous inquiries?
  • Hi Duke-san,

    I am sorry to my very late reply.
    I would like to send you the customer's circuit diagram (peripheral circuit diagram of DAC7716), so could you tell me your e-mail address or group mail address?

    By the way, the customer seems to set the output voltage range of the DAC7716 from -5 V to +5 V.
    2.5 V is applied as the reference voltage, and the gain is set to 4.
    The customer says that he is not using the calibration function and not setting the calibration register.

    Sincerely,
    M. Tachiaban
  • Tachibana-san,

    If it is okay with you I will email you at the address which you registered myTI.com account. From there we can continue the discussion.
  • Hi Duke-san,

    There is no problem with your proposal.
    If you send a e-mail to my address, I'll reply with the circuit diagram as attached file.

    Sincerely,
    M. Tachibana

  • Tachibana-san,

    Thanks!

    I apologize for the delays associated with the Thanksgiving Holiday in the US. I will email you now and we can continue the discussion there.